MARUTHI L N

Software Engineer

Bengaluru, Karnataka, India10 yrs 9 mos experience

Highly Stable

Key Highlights

Over 9 years of experience in verification and emulation engineering.
Expert in Universal Verification Methodology (UVM) and RTL verification.
Proven track record of enhancing system reliability and efficiency.

Stackforce AI infers this person is a Semiconductor Verification Engineer with expertise in RTL and emulation methodologies.

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Skills

Core Skills

Universal Verification Methodology (uvm)Assertion Based Verification

Other Skills

Coverage AnalysisC++VerilogMATLABPerlTclFunctional VerificationpythonCadence IMCQuestaSimc/c++velocevisualizerVerdisynopsys VCS

About

Verification and Emulation Engineer with over 9 years of experience in verifying and debugging digital designs and systems. Proven ability to work with different teams to solve design problems and meet project deadlines.

Experience

10 yrs 9 mos

Total Experience

3 yrs 6 mos

Average Tenure

3 mos

Current Experience

Amd

Member of Technical Staff

Mar 2026 – Present · 3 mos · Bengaluru, Karnataka, India · On-site

Qualcomm

Staff Engineer

Jun 2024 – Mar 2026 · 1 yr 9 mos · Bengaluru, Karnataka, India · On-site

Led verification and emulation for high-performance SoC designs using Mentor Graphics Veloce.
Developed and maintained C++ testbenches for SoC verification.
Prototyped emulation models to speed up verification and resolve issues early.
Evaluated test results to identify and address potential issues, enhancing the overall reliability and efficiency of the system.

Universal Verification Methodology (UVM)Coverage Analysis

Intel corporation

SoC Design Engineer

Nov 2017 – Jun 2024 · 6 yrs 7 mos · Bengaluru, Karnataka, India · On-site

Developed UVM-based testbenches for RTL verification of DSP blocks and simulated using VCS.
Collaborated in design reviews to ensure comprehensive code coverage.
Automated regression testing. Analyzed failed tests using waveform viewers and log files.
Executed concurrency test cases to ensure system stability under parallel processing conditions.
Set up and rectified issues in hardware emulation models for SOC’s (Synopsys ZeBu ZS3/ZS4/ZS5).
Developed multiple configurations of multi-chiplet emulation models on ZeBu.
Ran regressions and developed tests to replicate bugs found on silicon on the emulation model.
Integrated transactors and trackers into emulation models to expedite debugging.
Analyzed and identified root causes to minimize model size and enhance turnaround time.
Received 3 organizational awards, 6 departmental awards and other awards.

VerilogUniversal Verification Methodology (UVM)

Asarva chips & technologies pvt ltd

Design Verification Engineer

Sep 2015 – Nov 2017 · 2 yrs 2 mos · Bengaluru, Karnataka, India · On-site

Assisted in creating and running RTL simulations for WLAN PHY design using VCS.
Optimized MATLAB code by implementing MEX functions to enhance its execution speed.
Developed Perl and Tcl scripts to automate simulations.
Analyzed logs and waveforms to identify design flaws and verify functionality.
Performed extensive code coverage analysis to ensure thorough testing and validation.
Developed and implemented assertions for interrupt handling.
Developed noise channels to simulate real-time situations, enhancing the robustness and reliability of system
Prepared verification documentation and reported results to senior engineers and managers.

VerilogAssertion Based Verification