KHANG LÊ BÁ — Product Engineer
03/2025 - Present: working for Synopsys Vietnam as Design Verification Engineer. Experience Summary: - Build DV Environment with UVM Methodology, generate tests, debug failures, and evaluate coverage of design (Functional Coverage, Code Coverage, SVA). - Document test plans, testbench, and env. - Experience in both IP and Subsystem Level. - Experience with various protocol: AMBA (APB, AXI), high speed IP/Protocol (Ethernet). - Experience using VIP from Synopsys to verify DUT (ethernet VIP, AMBA VIP) - Programming skills: System Verilog, Verilog, C/C++, C-shell - Experience using EDA Tools: VCS/Verdi
Stackforce AI infers this person is a Design Verification Engineer with expertise in semiconductor and hardware verification.
Location: Ho Chi Minh City, Vietnam
Experience: 5 yrs 3 mos
Skills
- Design Verification
- Uvm Methodology
- Soc Design
Career Highlights
- Expert in Design Verification using UVM methodology.
- Proficient in multiple protocols including AMBA and Ethernet.
- Strong programming skills in System Verilog and C/C++.
Work Experience
Synopsys Inc
SoC Design Engineer (1 yr 3 mos)
Bach Khoa University (fomerly Ho Chi Minh City University of Technology)
Embedded Engineer (4 yrs)
