Kushagra Nainwal

Software Engineer

Bengaluru, Karnataka, India4 yrs experience
Highly Stable

Key Highlights

  • Expert in Silicon Design and Timing Analysis
  • Proficient in EDA tools and HDLs
  • Strong background in DRC checks and coverage debug
Stackforce AI infers this person is a Silicon Design Engineer with expertise in VLSI and EDA tools.

Contact

LinkedIn

Skills

Core Skills

Silicon DesignTiming AnalysisStatic Timing Analysis

Other Skills

DRC checksscan-chain setupscan and non-scan analysiscoverage debug & closuretiming debugcapture-timing simulationspattern generationfault modelspattern retargetingEDA toolsHDLs & scriptingAging simulations

Experience

4 yrs
Total Experience
4 yrs
Average Tenure
4 yrs
Current Experience

Amd

2 roles

Sr. Silicon Design Engineer

Promoted

Dec 2024 – Present · 1 yr 6 mos · Bengaluru, Karnataka, India

Silicon Design Engineer 2

Jun 2022 – Dec 2024 · 2 yrs 6 mos · Bengaluru, Karnataka, India

  • Core Skills
  • DRC checks, scan-chain setup
  • Scan and non-scan analysis; coverage debug & closure
  • Timing debug; capture-timing simulations
  • Pattern generation: UDFM, cell-aware, interconnect bridge/open
  • Fault models: timing-aware, path-delay, SAF, TDF
  • Pattern retargeting at top-SoC level across multi-IP environments
  • EDA tools: Synopsys TetraMAX, Verdi, VCS; PrimeTime; Mentor Tessent (TestKompress)
  • HDLs & scripting: SystemVerilog, Verilog, Python, Tcl
DRC checksscan-chain setupscan and non-scan analysiscoverage debug & closuretiming debugcapture-timing simulations+7

Stmicroelectronics

Project Trainee

Jun 2021 – May 2022 · 11 mos · Greater Noida, Uttar Pradesh, India

  • Worked in Smart Power (SPT) Department
  • Static Timing Analysis with Primetime
  • Aging simulations to compensate NBTI effects on CMOS.
Static Timing AnalysisAging simulations

Education

Indian Institute of Technology, Mandi

Master of Technology - MTech — VLSI

Jan 2020 – Jan 2022

College Of Technology, G.B.P.U.A&T, Pantnagar

Bachelor of Technology - BTech — Electrical Engineering

Jan 2015 – Jan 2019

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