Mahammed Hussain

Software Engineer

Bengaluru, Karnataka, India4 yrs experience

Highly StableAI Enabled

Key Highlights

Expert in Digital System Design and Mixed Signal IP.
Proficient in PCIe and Ethernet physical layer technologies.
Hands-on experience in ASIC design and RTL development.

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in ASIC and Mixed Signal IP.

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Skills

Core Skills

Digital System DesignPcie ProtocolAsic DesignRtl Development

Other Skills

LINT CDC RDC using VC SpyglassPCIe and Ethernet physical layerDigital system design using VerilogPTfishtailVclpFusion compilerATEpost silicone debugSerdes architecturePIPE specificationLint and CDCUPFSTASynthesis

Experience

4 yrs

Total Experience

4 yrs

Average Tenure

4 yrs

Current Experience

Synopsys inc

4 roles

Asic Digital Design Staff Engineer, Mixed signal IP (Multi protocol Serdes PHY)

Apr 2026 – Present · 2 mos · On-site

LINT CDC RDC using VC SpyglassPCIe and Ethernet physical layerDigital system design using VerilogPTfishtailVclp+14

Asic Digital Design Senior Engineer, Mixed signal IP (Multi protocol Serdes PHY)

Jan 2025 – Present · 1 yr 5 mos · On-site

Mixed signal IP, a Multi protocol Serdes PHY High Speed Interface) Senior Asic Design Engineer.

Digital system design using VerilogLINT CDC RDC using VC SpyglassPCIe and Ethernet physical layerPIPE specificationExposer to gentic AIDigital system design+1

Corporate Applications Senior Engineer, Mixed signal IP (Multi protocol Serdes PHY)

Promoted

Feb 2024 – Dec 2024 · 10 mos · On-site

SKILLS; PCIe physical layer, PIPE Spec and serdes architecture.

PCIe physical layerPIPE Specserdes architecture

Corporate Applications Engineer II, Mixed signal IP (Multi protocol Serdes PHY)

May 2022 – Feb 2024 · 1 yr 9 mos · On-site

PCIe protocolUPFPIPE specificationLint and CDCSTASynthesis+11

Intel corporation

Graduate Technical Intern

Aug 2020 – Jun 2021 · 10 mos · Bangalore Urban, Karnataka, India

Here I was part of ASIC on FPGA design team, working on Building chip to facilitate high speed Ethernet, my job was to hand all Qc flows such as
LINT
CDC
RDC
DESIGN CONSTRAINTS CHECK
DYNAMIC POWER &
SYNTHESIS
TOOLS HANDLED
Spyglass
Verdi and VCS
Power artist
Fishtail
DC topo.
Outcome:
Hands on experience in asic design and RTL development and sign off tools.