Jun 2023 – Jan 2026 · 2 yrs 7 mos · Bengaluru, Karnataka, India

• Leading physical design implementation and validation using Synopsys Fusion Compiler and DSO.ai to achieve best-in-class PPA for advanced nodes. Driving benchmarking initiatives to improve runtime, area, timing, and power across large-scale SoC designs. Partnering with cross-functional engineering teams to resolve critical design challenges and accelerate timing closure. Analyzing timing, clocking, and congestion to enhance overall design quality.
• Utilizing VS Code IDE for scripting, automation, and flow development to improve productivity and debugging efficiency. Validating new tool features and collaborating with R&D teams to provide actionable feedback, enabling enhancements in next-generation design flows.

Sep 2021 – May 2023 · 1 yr 8 mos · Bengaluru, Karnataka, India

• Physical Design Engineer with hands-on experience across key Backend IC design including Physical implementation, physical verification, and sign-off. Skilled in floorplanning, PnR, CTS, routing, timing closure, and ECO implementation for timing and functional fixes.
• Strong experience in PV flows (DRC, LVS, density checks, ICV), along with debugging and validation to achieve clean, tape-out quality sign-off. Focused on delivering high-quality designs with optimized performance and efficient closure.