Mar 2023 – Feb 2025 · 1 yr 11 mos · New Jersey, United States · Remote

• Primary Customer Support for Tier 1 Accounts: Assisted major North American customers in implementing high-speed, low-latency DSP applications on advanced FPGA platforms, including Versal, Ultrascale+, and other adaptive SoCs, ensuring successful deployment in complex environments.
• Timing Closure Expertise: Guided customers on synthesis, place & route, and static timing analysis and optimization, debugging critical timing issues in high-performance FPGA designs to ensure projects meet stringent latency and throughput requirements.
• AI Engine and DSP Algorithm Development: Designed and optimized AI Engine applications involving high-speed sorting, quantum error correction, matrix transforms, phased array antenna and packet processing, using both custom DSP algorithms and optimized IP blocks.
• Technical Troubleshooting and Debugging: Provided in-depth debugging support across diverse customer projects, tackling complex issues from DSP block integration, SystemVerilog Verification to cross-platform compatibility on Xilinx FPGAs.
• Documentation and Training: Authored detailed technical documentation and delivered training sessions on FPGA design best practices, focusing on DSP and AI Engine workflows for cross-functional engineering teams.
• #DSP #AI #ML #Versal #AIE

Nov 2021 – Mar 2023 · 1 yr 4 mos · United States · Hybrid

• Led Firmware Development: Served as Firmware Lead for the Link16/TACAN Terminal Tester project, managing all technical aspects of development.
• Leveraged RFSoC and Cryptography Expertise: Applied deep knowledge of Xilinx RFSoC platforms and cryptography to design Link16 and TACAN waveforms.
• Implemented Secure Crypto Systems: Developed an NSA certifiable Crypto Subsystem
• Engineered Secure Interfaces: Designed the DS101 fill port to ensure secure data handling and communication.
• Developed Advanced Firmware: Created NSA Crypto Management firmware using VHDL and SystemVerilog, including comprehensive testbenches.
• Collaborated with Software Teams: Provided C++ driver code to facilitate seamless integration with the software team.
• Managed Full Project Lifecycle: Directed all phases of the project, including requirements analysis, budgeting, VHDL coding/simulation, FPGA timing closure, and software development.
• Optimized Embedded Processing: Developed SystemVerilog testbenches, Coded and tested software in C++ for Microblaze and ARM processors, ensuring robust performance.
• Achieved Project Success: Completed the firm fixed price project under budget and ahead of schedule, showcasing effective project management and technical execution.

Jul 2016 – Nov 2021 · 5 yrs 4 mos · United States

• Led and Balanced Team Contributions: Successfully managed and mentored a team of eight FPGA engineers while maintaining an 80% hands-on development role.
• Delivered High-Impact Solutions: Served as the lead FPGA engineer on a $150M electronic warfare system program, architecting advanced FPGA solutions.
• Optimized High-Performance Designs: Achieved timing closure and integrated Ethernet IP for FPGA designs running at up to 375 MHz, leveraging Xilinx and Intel tools.
• Enhanced FPGA Testing Efficiency: Developed SystemVerilog testbenches and C++ software to test SoC-based FPGAs, ensuring robust performance and reliability.
• Collaborated Across Disciplines: Partnered with software and design teams to deliver state-of-the-art solutions tailored to system requirements.
• Adopted and Promoted DevOps: Implemented FPGA DevOps practices to streamline development processes and improve team efficiency.
• Mentored and Recruited Talent: Mentored team members and actively participated in recruitment to strengthen engineering capabilities.
• Recognized for Technical Leadership: Earned multiple awards for outstanding contributions and leadership in technical and project domains.

Oct 2015 – Jun 2016 · 8 mos

• Paid Non-compete period from Susquehanna. Completed security clearance process for L3Harris role while on garden leave.

Apr 2014 – Sep 2015 · 1 yr 5 mos

• Architected and Designed Trading Technology: Led the architecture and design of FPGA-based options market making and taking technology across multiple exchanges.
• Developed Market Data Parsers: Designed options market data parsers and order execution managers for exchanges including BATS, MIAX, NOM, ISE, and ARCA using VHDL and SystemVerilog.
• Achieved Industry-Leading Latency: Implemented electronic eye strategies with ultra-low latency, achieving over 90% fill rates.
• Enhanced Platform Performance: Improved platform components such as TCP/IP offload engines, DRAM, and PCI Express DMA controllers, optimizing overall system efficiency.
• Improved Order Fill Rates: Boosted fill rates from 20% to 96% at MIAX, the fastest options exchange at the time.
• Set Industry Standards: Contributed to developing the fastest trading systems across deterministic latency exchanges, solidifying a competitive edge in the market.
• Architected order routing gateway that allowed combining quoting traffic with proprietary trading orders to allow for those orders to have higher priority at the exchange matching engine.

Aug 1991 – Sep 2014 · 23 yrs 1 mo · United States · On-site

• ARTHATECH, Metuchen, NJ, Chief Technology Office
• CREDIT SUISSE, New York, NY, FPGA Consultant (VP Level), Investment Banking IT, Global Arbitrage Trading
• TEL INSTRUMENTS, East Rutherford, NJ, Principal FPGA Engineer (Contract)
• TECHNICOLOR, Princeton, NJ, Senior Research Engineer, Corporate Research Lab
• VILLAGE NETWORKS, Eatontown, NJ, Principal Hardware Engineer
• 3COM, Holmdel, NJ / Santa Clara, CA, Senior Hardware Engineer, Mobile Products Division