Mayank Agarwal

Software Engineer

Noida, Uttar Pradesh, India20 yrs 4 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Expert in ASIC and VLSI design and verification.
  • Proven track record in functional verification methodologies.
  • Strong background in low-power design techniques.
Stackforce AI infers this person is a VLSI and ASIC design expert with extensive experience in functional verification.

Contact

mayank.bangalore@gmail.comLinkedIn

Skills

Core Skills

AsicVlsi

Other Skills

SystemVerilogFunctional VerificationVerilogStatic Timing AnalysisSoCPhysical DesignRTL designRTL verificationLogic DesignLow-power DesignTCLEDAOpen Verification MethodologyProcessorsPrimetime

Experience

20 yrs 4 mos
Total Experience
2 yrs 10 mos
Average Tenure
7 yrs 4 mos
Current Experience

Qualcomm

Senior Staff Engineer

Jan 2019 – Present · 7 yrs 4 mos

SystemVerilogASICVLSIFunctional VerificationVerilogStatic Timing Analysis+13

Nxp semiconductors

Principal Engineer

Jan 2017 – Jan 2019 · 2 yrs

Broadcom

Sr Staff Engineer

Jan 2013 – Jan 2017 · 4 yrs

Advanced micro devices

Member of Technical Staff

Jan 2010 – Jan 2013 · 3 yrs

Intel

Component Design Engineer

Jan 2008 – Jan 2010 · 2 yrs

  • Graphics Division, Front End Design and Verification.

Montalvo systems

Design Engineer

Jan 2007 – Jan 2008 · 1 yr

  • Worked on Processor Performance Verification & Analysis and Emulator Systems Validation Framework.

Vitesse semiconductor

Design Engineer

Jan 2006 – Jan 2007 · 1 yr

  • I worked for RTL Verification, Network Standards Compliance and DV environment migration from Vera to SystemVerilog.

Education

International Institute of Information Technology Hyderabad (IIITH)

MS (by Research) — VLSI & Embedded Systems

Jan 2004 – Jan 2006

RV College Of Engineering

B. E. — Electronics and Telecommunication

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