Jul 2009 – Feb 2021 · 11 yrs 7 mos · Kawasaki

• I developed the design implementation methodologies, design kits using EDA vendor tools and deployed them and support worldwide design centers (North America, Europe and Japan). I mainly focused to realize true RTL2GDS flow to improve Toshiba SoC performance, productability, to reduce SoC development cost and TAT.
• I always researching/evaluating the latest EDA tools to find out those have sharpen feature/potential or not . I lead worldwide design teams to realize skilled engineers.
• Here is the list I deployed and/or improved design environment and tools ;
• Orion DK (Synopsys/ICC1) design environment (improved), for entire SoC design
• FFSA DK (Cadence/EDI) design environment, for Toshiba uniq FFSA
• DC-DK (Synopsys / DC and DCG), for synthesis including physical
• RC-DK (Cadence/RTL Compiler), for logic synthesis
• Genus-DK (Cadence / Genus-Physical) design environment, for physical synthesis
• Orion-Academic (Synopsys / ICC1) for VDEC, for design labs at college
• Orion-COT (Synopsys / ICC1) for COT customers, for Toshiba Fab customers
• EDI-COT (Cadence / EDI) for COT customer, for Toshiba Fab customers
• Polaris (Synopsys / StarRC and PT) for timing S/O
• Kadlu (Synopsys / Prime Power), for power verification
• Tachyon DS (Synopsys / Fusion Compiler, ICC2, Formality, VCLP, in-design ICV, Prime Rail), this handles “true RTL2GDS flow” in single cockpit.
• I handled several SoC applications such as networking, ASSP, mobile, HPC, ASICs, MCU and image sensor. And I ran technology transfer from Japan side to worldwide design centers.

Feb 2000 – May 2009 · 9 yrs 3 mos · San Jose

• I mainly developed the design implementation methodologies, design kits using EDA vendor tools and
• Deployed them and support worldwide design centers (North America, Europe and Japan).
• I always searching the latest EDA tools which have sharpen feature/potential. I lead worldwide design teams to realize skilled engineers.
• Here is the list I deployed design environment and tools ;
• First Encounter feasibility/prototyping environment
• Physical Compiler physical optimization design environment
• Pinnacle design kit(Cadence/SOCEncounter) design environment
• Apex Design System (MAGMA/BlastFusion) design environment
• Sierra/Pinnacle design environment
• In Design-Brion Litho-Simulation and fixing environment on BlastFusion
• Get2Chip Logic optimization environment
• NonoRoute routing solution
• I handled several SoC area such as networking, ASSP, mobile, HPC and ASICs, And I ran technology transfer from Japan side to worldwide design centers.

Apr 1991 – Jan 2000 · 8 yrs 9 mos · Kawasaki

• I researched/developed Toshiba In-house physical implementation tools. Those are ChipIn for Gate-array and ChipMaster for standard cell technology. My main area is placement, floor planning, database management, low power implementation method, user supporting and actual SoC designing. I deployed the design environment of ChipIn/ChipMaster for Toshiba design centers (North America, Europe and Japan). Early phase of ChipIn/ChipMaster deployment, I evaluated EDA vendor tools to use as supplemental tool for ChipIn/ChipMaster and deployed them. Those are Silbar Lisco/Gards (line-search-router) and Cadence/Gate Ensemble router.