muralikumar jha

Software Engineer

Mumbai, Maharashtra, India6 yrs 9 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

7+ years in ASIC/SOC design verification.
Expert in System Verilog and UVM methodologies.
Proven track record in complex verification projects.

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in ASIC and SOC verification.

Contact

Skills

Core Skills

System VerilogUvmAsic DesignVerificationRtl DesignDesign Verification

Other Skills

TestBench EnvironmentTest PlanTestbench ArchitecturesScoreboardSequenceCoverage CollectorAssertion Based CheckersCNN NPUVerification Requirement SheetUVM Based EnvironmentAssertionsSanity TestingRegression TestingCode CoverageFunctional Coverage

About

Design and verification engineer with 7+ years of experience in critical engagements like IP/SOC/ASIC Design Verification using System Verilog and UVM with hands-on for AMBA protocols like AXI, AHB, APB, I2C and PCIE v5 Transaction layer. Top Key Skills: ➢ ASIC & SOC design and verification . ➢ System Verilog and UVM. (for verification) ➢ Coverage Driven Verification. ➢ System Verilog Assertion Based Verification. ➢ Code Coverage & Functional Coverage. ➢ Verilog HDL (RTL Design ). ➢ FPGA Design & Verification . ➢ Knowledge Of C, C++, Linux/Shell and Perl Scripting. ➢ Advance Digital Design. ➢ Worked on Tools like: Questasim , Modalsim. VCS, Verdi ,Xilinx ISE , Xilinx VIVADO Contact : 8286709022 Email: muralikumarjha1995@gmail.com

Experience

6 yrs 9 mos

Total Experience

1 yr 4 mos

Average Tenure

3 yrs 10 mos

Current Experience

Amd

2 roles

Sr. Silicon Design & Verification Engineer

Promoted

Nov 2024 – Present · 1 yr 7 mos · Hybrid

Silicon Design & Verification Engineer -2

Aug 2022 – Nov 2024 · 2 yrs 3 mos · Hybrid

Experience in Developing in UVM based TestBench Environment.
Test Plan and testbench architectures development.
Experience in developing of Scoreboard, sequence, coverage collector, assertion based checkers.

UVMTestBench EnvironmentTest PlanTestbench ArchitecturesScoreboardSequence+3

Marquee semiconductor inc.

ASIC/IP Design & Verification Engineer- 1

Apr 2021 – Aug 2022 · 1 yr 4 mos · Bhubaneswar, Odisha, India

Experience #5: ASIC Design and Verification of CNN Neural Processing Unit (NPU)
ASIC Design Verification of CNN (convolution neural network Based AI processor) of NPU(Neural Processing Unit)
Contribution :-
o Verification of Main Arbiter (MARB) of NPU(Neural Processing Unit).
o Understood the Main Arbiterspecifications.
o Developed Verification Requirement Sheet (Test Plan) .
o Developed UVM Based environment .
o Scoreboard and Checkers(assertions) .
o Multiple test scenario for verifying the functionality of the Main Arbiter .
o Sanity and Regression testing, Makefile , run_script .
o Code coverage and implemented the functional coverage.
o Analyzed the reports and excluded the unwanted signals, modules.
o Debugging DUT errors and filed bugs in bug tracker
Experience #4: PCIe (RC-DUT) Verification
Contribution :-
o Understood the TX Layer specifications.
o Understanding the environment flow .
o Sanity testing and Regression testing .
o Implemented some basic test ,
o Implemented different types of error injection test scenarios.

ASIC DesignVerificationCNN NPUVerification Requirement SheetUVM Based EnvironmentScoreboard+5

Algowire technologies

RTL Design & Verification Engineer (6 month Contract)

Oct 2020 – Mar 2021 · 5 mos · Noida, Uttar Pradesh, India

1)RTL Design of Network data receiver module on net_clk. (Live project)
2)Utilization of GTY transceiver ip core in main project for transmit and receive channel.
3)Development of Testbench for RTL Verification & RTL simulation .
4) RTL optimization & Debugging.
5)RTL Design of data receiver module using AXI-4 Stream interface . (Live project)

RTL DesignVerificationTestbench DevelopmentRTL OptimizationDebuggingAXI-4 Stream Interface

Cdac

Design Verification Engineer

Aug 2019 – Mar 2020 · 7 mos · Mumbai, Maharashtra, India

1)VIP development of APB and verification of APB interface based SRAM.
2)VIP development of I2C .
3)RTL Design and Verification of Async FIFO.
4)knowledge of AHB/APB/I2C
5)shell scripting, Makefile,
6)RTL/FPGA/ASIC/SOC design and verification

VIP DevelopmentAPBI2CRTL DesignVerificationShell Scripting+2

Indiabulls real estate

Electronics Engineer

Dec 2018 – Aug 2019 · 8 mos · Mumbai Area, India

Work Experience:
Job responsibility -:
Established the physical connection between the divides by Ethernet cable (using Ethernet protocol)
Testing the devices & observed the Transaction & also timing synchronization of the devices.
Testing the devices according to its functionality whether it meets the requirement or not.
Configure the all the devices with a server & test its functionality, whether it is able to
communicate with one another or not.
Make an Excel file & list all the testing scenario of functionality and mark them whether it pass or fail. Integrating the access control system(hardware) with software and configure the device with IP address

Eviska infotech pvt. ltd.

Electronic Engineer

Jun 2018 – Dec 2018 · 6 mos · Mumbai Suburban, Maharashtra, India

Job responsibility -:
Established the physical connection between the devices (using Ethernet protocol)
Testing the devices & observed the Transaction & also timing synchronization of the devices.
Testing the devices according to its functionality whether it meets the requirement or not.
Configure the all the devices with a server & test its functionality, whether it is able to
communicate with one another or not.
Make an Excel file & list all the testing scenario of functionality and mark them whether
it pass or fail.