Navika Iyer — Software Engineer
Strong professional with a Master of Science - MS focused in Electrical and Electronics Engineering from San Jose State University. Skilled in Universal Verification Methodology (UVM), SystemVerilog, Application-Specific Integrated Circuits (ASIC), Verilog and Computer Architecture.
Stackforce AI infers this person is a Systems Design Engineer with expertise in ASIC and VLSI technologies.
Location: San Jose, California, United States
Experience: 7 yrs
Career Highlights
- Master's degree in Electrical and Electronics Engineering.
- Expertise in Universal Verification Methodology and SystemVerilog.
- Strong background in ASIC and Computer Architecture.
Work Experience
Sandisk
Staff Engineer, Systems Design Engineering (2 yrs)
Western Digital
Senior Engineer, Systems Design Engineering (3 yrs 4 mos)
San Jose State University
Research Assistant (5 mos)
Teaching Associate (9 mos)
Sagacious IP
Patent Analyst - Intern (6 mos)
Education
Master of Science - MS at San José State University
Bachelor of Technology - BTech at The NorthCap University
High School Diploma at Delhi Public School, Dwarka
