Nishita Bodawala — Software Engineer
Completed Mtech(2018-2020) in Digital Electronics and Communication Engineering from Manipal Academy of Higher Education. Former Design Verification Intern at Mirafra Software Technologies Pvt. Ltd. having experience in System Verilog and UVM testbench creation, Functional Coverage using Constrained randomization testing and also Regression Testing.
Stackforce AI infers this person is a VLSI Verification Engineer with strong skills in ASIC design and verification methodologies.
Location: Bengaluru, Karnataka, India
Experience: 4 yrs 1 mo
Skills
- Universal Verification Methodology (uvm)
- Functional Verification
- Systemverilog
Career Highlights
- Expertise in UVM and SystemVerilog for ASIC verification.
- Hands-on experience in functional coverage and regression testing.
- Strong educational background in Digital Electronics and Communication.
Work Experience
MediaTek
ASIC Verification Engineer (4 yrs)
Mirafra Technologies
Design Verification Intern (10 mos)
Space Applications Centre, ISRO
Research Intern (3 mos)
Education
Master of Technology - MTech at Manipal Academy of Higher Education
Bachelor of Technology - BTech at Dharmsinh Desai University
