Dharmesh Gurjar — Software Engineer
I have 3.5+ years of experience in the Design and verification Domain. Currently working on UCIe controller IP and subsystem Verification. Also I have worked on PCIe(PHY layer verification) and CXL2.0(LInk Layer and ARB/MUX Layer verification) with the demostrated history of working with different industry standard tools and technology. I am highly Self Motivated and commited entry level engineer who is eager to learn new things, Having Good analytical and Communication Skill. Skills:- 1) HVL Language - Verilog and SystemVerilog 2) Verification Methodology - UVM 3) Constraints Random Verification 4) System Verilog Coverage(SVG) 5) System Verilog Assertion(SVA) 5) Shell/Perl Scripting Experience in industry Protocol. 1) UCIe 2)AHB2APB Bridge 3)AHB 4)AXI (Specification understanding) 5)PCIe 5.0(PHY Layer verification) 6)CXL 2.0(Link Layer and ARB/MUX Layer verification) Interests are Digital Electronics & Computer Hardware, ASIC Design and Functional Verification, Scripting.
Stackforce AI infers this person is a Design Verification Engineer with expertise in ASIC and digital electronics.
Location: Surat, Gujarat, India
Experience: 6 yrs
Career Highlights
- 3.5+ years in Design and Verification domain
- Experience with UCIe, PCIe, and CXL2.0 protocols
- Proficient in Verilog, SystemVerilog, and UVM
Work Experience
Qualcomm
Senior Design Verification Engineer (1 yr 3 mos)
Cadence Design Systems
Design Engineer II (1 yr 9 mos)
eInfochips (An Arrow Company)
ASIC Design Verification Engineer (1 yr 7 mos)
eiTRA - eInfochips Training & Research Academy Ltd
Project Trainee -ASIC (6 mos)
The Maharaja Sayajirao University of Baroda
Training and Placement Cell Coordinator (11 mos)
Education
BE - Bachelor of Engineering at The Maharaja Sayajirao University of Baroda
Higher Secondary at P. P. SAVANI VIDHYA SANKUL
