Parabrahmam Madamanchi

Engineering Manager

Bengaluru, Karnataka, India13 yrs 2 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Expert in PCIe domain with extensive verification experience.
  • Proven leadership in complex mixed signal design projects.
  • Skilled in developing advanced verification environments.
Stackforce AI infers this person is a Mixed Signal Verification Engineer with a strong focus on PCIe technologies.

Contact

LinkedIn

Skills

Core Skills

PcieSilicon ValidationSystemverilogMixed Signal

Other Skills

Technical Project LeadershipVerilogOVMI2CI2SAHBSpyglassTeam BuildingCross-functional CoordinationCross-functional Team LeadershipProject PlanningASICCOpen Verification MethodologyNCSim

About

PCIe domain expertise, Mixed signal design verification. Development of complex test benches in SV & UVM. Technical lead & functional verification closure.

Experience

13 yrs 2 mos
Total Experience
6 yrs 7 mos
Average Tenure
11 yrs 8 mos
Current Experience

Nvidia

2 roles

Engineering Manager

Promoted

May 2025 – Present · 1 yr 1 mo · On-site

  • PCIe physical and data link layer verification.
PCIeSilicon ValidationTechnical Project Leadership

Senior ASIC Verification - Lead

Oct 2014 – May 2025 · 10 yrs 7 mos · On-site

  • PCIe domain expert.
  • Experience in PL, DL and TL layer verification.
  • Worked on multiple PCIe generations from Gen3 to Gen6.
SystemVerilogVerilogPCIe

Aura semiconductor

ASIC Verification Engineer

Mar 2013 – Sep 2014 · 1 yr 6 mos · Bangalore · On-site

  • Analog Mixed Signal Designs (PLLs, DSP filters, Audio Designs, Clocks Designs)
  • 1. Creating verification environment flows from scratch, using OVM-System Verilog
  • 2. Mat-lab to C-Models translation.
  • 3. Analog Models Development.
  • 4. I2C, I2S, AHB interfaces verification.
  • 5. Develop scripts for regressions.
OVMSystemVerilogI2CI2SAHBMixed Signal

Lsi, an avago technologies company

Project Trainee

Feb 2012 – Jan 2013 · 11 mos

  • 12 months internship in Design and Verification in FCD division in Pune.
  • Spyglass issues cleanup.
  • Designed encoder & decoders.
  • Then moved to verification using System verilog.
  • Worked on AHB register interface verification.
SystemVerilogSpyglass

Education

CDAC ACTS

DIVESD — VSLI and Embedded Systems

Jan 2011 – Jan 2012

CVSR College of Engineering

B.Tech — Electronics and Communication Engineering

Jan 2007 – Jan 2011

Sri Gowthami Jr College

Intermediate — MPC

Jan 2004 – Jan 2006

Sri Saraswathi High School

SSC — Mathematics and General Science

Jan 2003 – Jan 2004

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