Dhaval Patel

Director of Engineering

Bengaluru, Karnataka, India13 yrs 2 mos experience

Key Highlights

Expert in GPU design verification and management.
Proven track record in functional verification methodologies.
Strong leadership in managing verification teams and projects.

Stackforce AI infers this person is a Semiconductor Verification Expert with a focus on GPU and power management.

Contact

Skills

Core Skills

Functional VerificationUniversal Verification Methodology (uvm)Power Management VerificationAxi Protocol Verification

Other Skills

GPU DVpixel pipe verificationcontrol subsystem verificationAddress library verificationcolor block IP verificationteam managementderivative project managementverificationCstate power managementSstate power managementtestplan ownershiptestcase developmentchecker implementationscoreboard creationfunctional coverage

About

- Hardware Description Language: Verilog HDL. - High level Verification Language: System Verilog - Hardware Architectures: AXI, APB, AHB,Basics of Nvme,GPU - Methodology known: UVM, Basics of VMM. - Scripting Languages: Perl Scripting, Shell Scripting. - EDA Tools: QuestaSim, VCS, ISE (Xilinx), Cadence simvision. - Programming Languages: C, C++. - Operating Systems: Linux, Windows. - Experience in Constrained Random Verification and writing the assertions. - Experience in running regression and coverage reports. - Experience in working with bug tracking tools JIRA, documentation tool confluence. - Knowledge of SVN, Perforce repository. - Experience in working with design sync repository.

Experience

13 yrs 2 mos

Total Experience

Average Tenure

Current Experience

Samsung semiconductor

2 roles

Associate Director

Promoted

Mar 2025 – Present · 1 yr 3 mos · Bengaluru, Karnataka, India · Hybrid

Senior Staff/ Engineering Manager

Apr 2022 – Mar 2025 · 2 yrs 11 mos · Bengaluru, Karnataka, India · Hybrid

GPU DV:
Leading pixel pipe and control subsystem.
Owning Address library and color block IP verification.
Managing a 7 member team.
Leading Derivative project for 7 mega blocks verification.

GPU DVpixel pipe verificationcontrol subsystem verificationAddress library verificationcolor block IP verificationteam management+3

Amd

Senior Silicon Design Engineer

Sep 2018 – Apr 2022 · 3 yrs 7 mos · bangalore · On-site

Worked in the infinity data fabric power management IP level team.
Worked on Cstate and Sstate power management state machine verification.
Ownership of complex power management testplan, testcases, checker, scoreboard and functional coverage.
Ownership of derivative project execution.

Cstate power managementSstate power managementtestplan ownershiptestcase developmentchecker implementationscoreboard creation+3

Nxp semiconductors

Verification Consultant

Mar 2017 – Sep 2018 · 1 yr 6 mos · Noida Area, India

> PROJECT TITLE: BLOCK LEVEL AND SUBSYSTEM VERIFICATION OF LLCE.
Block level Verification:
Worked on block level verification of LLCE TX QUEUE ACCELATOR(TX_LUT) and Interrupt concentrator and router(IC-IRCM) from scratch.
Developed block level verification environment in UVM as well as UVM RAL model from scratch.
Experience on writing assertions for TX_LUT and IC-IRCM.
Implemented functional coverage model with cross coverage on block level.
Achieved 100% code coverage for TX_LUT, IC and IRCM blocks.
Sub-system level Verification:
Worked on subsystem level verification on llce_top.
Ported assertions and functional coverage from block level to subsystem level.
Implemented data flow loopback test for linflex transmit and receive path.
Developed C-testcase to verify register accessibility for all the blocks on llce_top.
Simulator : Cadence simvision
Languages : System Verilog with UVM methodology

block level verificationsubsystem level verificationUVMassertion writingfunctional coveragetest environment development+2

Perfectvips

ASIC Verification engineer

Oct 2016 – Sep 2018 · 1 yr 11 mos · Ahmedabad, Gujarat, India

Aumraj design systems

ASIC Verification Engineer

Mar 2013 – Sep 2016 · 3 yrs 6 mos · Greater Ahmedabad Area

> PROJECT TITLE: VERIFICATION OF CONFIGURABLE AXI-INTERCONNECT.
Responsible for verifying designs for AXI data width converters.
Responsible for verifying protocol conversion for read-write transactions. (APB to AXI, AHB to AXI and vice-versa).
Implemented configurable protocol, data width, number of masters-slave AXI interconnect.
Implemented an automated run script for compilation and simulation.
Simulator : QuestaSim
Languages : System Verilog with UVM methodology
Time Duration : March 2016 to September 2016.
> PROJECT TITLE: VERIFICATION OF HDPS SUBSYSTEM ENVIRONMENT.
Developed HDPS Sub system level verification environment in UVM.
Implemented top level loopback test with data compression, encryption features.
Implemented functional coverage for top level parameters.
Completed the whole top level verification process cycle.
Implemented the verification test-plan and test scenarios for subsystem level.
Responsible to develop sequences as per test plan, run regression, debug failures.
Simulator : QuestaSim
Languages : System Verilog with UVM methodology
Time Duration : September 2014 to March 2016.
> PROJECT TITLE: PORTING OF BALBOA FLASH MEMORY CONTROLLER FROM VMM TO UVM.
Developed UVM test bench environment flow architecture from VMM.
Ported the whole balboa VMM environment to UVM environment.
Implemented and maintaining the sequences and test cases in UVM.
Created and updated the Perl Script at different phase of project cycle.
Responsible to run regression, debug failures.
Simulator : QuestaSim, VCS.
Languages : System Verilog with UVM methodology, VMM.
Time Duration : September 2013 to August 2014.

AXI data width convertersprotocol conversionautomated run script implementationFunctional VerificationAXI Protocol Verification

Eitra - einfochips training & research academy ltd

ASIC Verification Training

Jan 2012 – Jul 2012 · 6 mos · Greater Ahmedabad Area

Hands on experience in linux, perl and shell scripting language.
Verilog : In Depth Knowledge of Verilog, Blocking-Non Blocking Assignment, Task, Function,Always block, Initial block, Inter Assignment Delay,Intra Assignment Delay,Good understanding of Race condition, Thoroughly Studied Cliff Cummings Papers.
System Verilog : In Depth Knowledge of System Verilog,Array Data Types, Connecting the Design and Testbench, Interface,Randomization, Basic OOP Concepts, Functional Coverage