P

Parthasarathi Duddukuru

Software Engineer

Bengaluru, Karnataka, India5 yrs 8 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Expert in low power design implementation.
  • Proficient in automated scripting with Tcl.
  • Strong background in physical design methodologies.
Stackforce AI infers this person is a Physical Design Engineer with expertise in semiconductor technology.

Contact

dpsparthu333@gmail.comLinkedIn

Skills

Core Skills

Place & RouteLow Power Design

Other Skills

FloorplanningClock Tree SynthesisTcl scriptingStatic Timing AnalysisDigital ElectronicsLinuxC ProgrammingPythonSynopsys PrimetimeIR AnalysisPhysical VerificationSynopsys FormalityLow Power - VCLPPD CADPnR

About

• Taped out SOC blocks at 5nm tech node from RTL2GDS • Thorough understanding of AMD PnR flow and Implemented new methodologies • Low power design implementation - MV and ONO blocks • Strong understanding of upf • Floorplanning of high macro count • Clock spec file to control timing with CTS • Automated daily tasks using Tcl in ICC2 • Signoff - Timing, LEC, VCLP, PV, IR closure Tools Exposure : ICC2, Primetime, vc static, Formality, Calibre Scripting : Tcl, Unix, Perl, python

Experience

5 yrs 8 mos
Total Experience
1 yr 5 mos
Average Tenure
1 yr 8 mos
Current Experience

Samsung semiconductor

Associate Staff Physical Design Engineer

Oct 2024 – Present · 1 yr 8 mos · Bengaluru, Karnataka, India · Hybrid

Place & RouteLow Power DesignFloorplanningClock Tree SynthesisTcl scriptingStatic Timing Analysis+2

Soctronics

Physical Design Engineer

Aug 2021 – Oct 2024 · 3 yrs 2 mos · Hyderabad, Telangana, India

Veda iit

Physical Design Engineer Trainee

Feb 2021 – Jul 2021 · 5 mos · Hyderabad

Cognizant

BigData Analyst Trainee

Aug 2020 – Jan 2021 · 5 mos · Chennai, Tamil Nadu, India

C ProgrammingPython

Iiitdm kancheepuram

VLSI Internship

Dec 2019 – May 2020 · 5 mos · kandigai

Education

Sree Vidyanikethan Engineering College

Bachelor of Technology

Jan 2016 – Jan 2020

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