Peng Y.

Associate Consultant

Sydney, New South Wales, Australia16 yrs 5 mos experience

Highly Stable

Key Highlights

Nearly two decades in semiconductor and VLSI sectors.
Expert in formal verification with proven methodologies.
Dedicated to empowering learners through customized training.

Stackforce AI infers this person is a formal verification expert in the semiconductor industry.

Contact

Skills

Core Skills

Formal Verification

Other Skills

SimulationDigital IC DesignEDAVery-Large-Scale Integration (VLSI)Application-Specific Integrated Circuits (ASIC)

About

Greetings, I am Peng Yu, an industry veteran with close to two decades of experience in the semiconductor and VLSI sectors, focusing on digital circuit design and verification, as well as EDA tool application and design fields. For 14 years, I contributed to Cadence, a leading EDA vendor, specializing in providing technical support for formal verification. Currently, I serve as a senior staff technical consultant in formal verification at a startup, where my role encompasses a wide array of responsibilities. These include the development of formal verification IP, creation of online courses on platforms like eda-academy.com, consultation on formal verification technical matters, provision of customized training for individuals and businesses, and delivery of professional formal verification outsourcing services for companies. With my extensive background and expertise, I am dedicated to sharing my knowledge and insights with learners at EDA Academy, empowering them to excel in the field of formal verification.

Experience

16 yrs 5 mos

Total Experience

13 yrs 6 mos

Average Tenure

2 yrs 11 mos

Current Experience

Eda academy

Senior Staff Technical Consultant in Formal Verification

Jul 2023 – Present · 2 yrs 11 mos · Remote

Working as a senior staff technical consultant in formal verification, where my role encompasses a wide array of responsibilities. These include the development of formal verification IP, creation of online courses on platforms like eda-academy.com, consultation on formal verification technical matters, provision of customized training for individuals and businesses, and delivery of professional formal verification outsourcing services for companies.
With my extensive background and expertise, I am dedicated to sharing my knowledge and insights with learners at EDA Academy, empowering them to excel in the field of formal verification.
My goal is to share this expertise with students at EDA Academy, providing them with practical insights and industry best practices that they can apply directly to their own projects. By imparting this knowledge, I aim to empower learners to achieve their verification goals with confidence and efficiency.

Formal VerificationSimulation

Cadence design systems

Senior Principal Application Engineer

Dec 2009 – Jun 2023 · 13 yrs 6 mos

With a wealth of experience in formal verification projects, I specialize in two critical solutions: formal signoff with full proof and formal signoff with coverage. Throughout my career, I have successfully tackled a diverse range of designs, including Instruction units, Standard interfaces, User-defined interfaces, Bus matrices, Caches, MMUs, Schedulers, DMA controllers, Memory controllers, Interrupt controllers, Power management units, and various specific functional modules.
One of my key achievements has been the independent creation of a comprehensive formal verification IP library. This library comprises nearly 200 units, encompassing basic, common, VIP, and flow libraries. These resources, combined with my methodology, have been successfully deployed in the product development workflows of numerous leading chip companies. The results speak for themselves, with significant improvements in verification effectiveness and performance observed across the board.
Drawing on this extensive project experience and a deep understanding of various design types, I have developed a unique formal verification methodology. This methodology has been honed through practical application and has proven highly effective in ensuring design correctness and efficiency.

Digital IC DesignSimulationFormal Verification