Piyush Bhangale

Software Engineer

Bengaluru, Karnataka, India2 yrs 11 mos experience
Highly Stable

Key Highlights

  • Ambitious Design Verification Engineer at Qualcomm.
  • Strong foundation in VLSI and digital design.
  • Hands-on experience with leading verification methodologies.
Stackforce AI infers this person is a VLSI Design Verification Engineer with a focus on semiconductor technology.

Contact

LinkedIn

Skills

Core Skills

Functional VerificationSystemverilogVhdl

Other Skills

AMBA AHBLinuxXilinx ISESystem on a Chip (SoC)Test PlanningDigital Circuit DesignC (Programming Language)VerilogC++MATLABPIC ProgrammingMicrosoft ExcelMicrosoft OfficeLeadershipInterpersonal Skills

About

An ambitious, driven individual with a great interest in the field of VLSI

Experience

2 yrs 11 mos
Total Experience
2 yrs 11 mos
Average Tenure
2 yrs 11 mos
Current Experience

Qualcomm

3 roles

Engineer

Dec 2025 – Present · 6 mos

Associate Engineer

Jun 2023 – Nov 2025 · 2 yrs 5 mos

AMBA AHBFunctional Verification

Interim Engineering Intern

Jan 2023 – Jun 2023 · 5 mos

LinuxSystemVerilog

Isro - indian space research organization

Hardware Engineering Intern

May 2022 – Jul 2022 · 2 mos · Bengaluru, Karnataka, India

Xilinx ISEVHDL

Team unwired

Motor and Transmission Engineer

Sep 2020 – Apr 2022 · 1 yr 7 mos · Kozhikode, Kerala, India

Education

National Institute of Technology Calicut

Bachelor of Technology - BTech — Electrical and Electronics Engineering

Jan 2019 – Jan 2023

Jawahar Navodaya Vidyalaya - JNV

Science

Jul 2012 – May 2019

Stackforce found 100+ more professionals with Functional Verification & Systemverilog

Explore similar profiles based on matching skills and experience

K S D PRASAD

K S D PRASAD

ASIC Verification Engineer

at Radiant Semiconductors Pvt.Ltd

East Godavari, India4 yrs 1 mo exp
RTL VerificationUniversal Verification Methodology (UVM)RTL Design
SS

Sudheera S P

Customer Support Engineer

at Cisco Systems (India) Private Limited, Bangalore

Edinburgh, United Kingdom9 yrs 2 mos exp
Routing and SwitchingNetwork ConfigurationNetwork Design
Aakash Gupta

Aakash Gupta

Senior Engineer

at Synopsys Inc

Greater Delhi, India4 yrs 3 mos exp
Logic SynthesisFormal Equivalence Verification
Bharadwaj K

Bharadwaj K

Senior Network Consulting Engineer (Network Consulting Engineer IV)

at Cisco

Bengaluru, India7 yrs 7 mos exp
NetworkingCommunication
Gagandheep Raikar

Gagandheep Raikar

ASIC Digital Design Senior Engineer

at Synopsys Inc

Bengaluru, India3 yrs 10 mos exp
Digital Design
Mahesh Palaka

Mahesh Palaka

FPGA Silicon Design Verification Engineer

at Altera

Bengaluru, India1 yr 2 mos exp
VerificationVLSISoftware DevelopmentIP DesignDigital Design
G Shiva Prasad

G Shiva Prasad

Embedded Design Engineer

at Healthcare Technology Innovation Centre

Chennai, India4 yrs exp
Embedded SystemsFirmware
Vishal Suman

Vishal Suman

Senior Engineer at Sandisk

at Sandisk

Bengaluru, India7 yrs 4 mos exp
RTL DesignField-Programmable Gate Arrays (FPGA)Design