Prakash Saw — Software Engineer

As a passionate and technically driven VLSI engineer with a master’s from IIT Mandi, I specialize in physical design and static timing analysis (STA) for high-performance ASICs. At Qualcomm, I’ve worked on critical blocks where timing closure, area optimization, and power integrity were mission-critical — and delivered measurable improvements. • Expertise: Floorplanning, power-grid (PDN) design, placement, clock-tree synthesis (CTS), and parasitic-aware optimization. • Technical Stack: Proficient with Cadence and Synopsys EDA tools, Python/Tcl scripting, and UPF-based low-power design. • Achievements: • Accelerated timing convergence in a multi-corner design, reducing overall slack violations by 25%. • Improved power-grid robustness, cutting worst-case IR drop by 15% through optimized strap placement. • Designed and verified CTS trees across multiple voltage domains, achieving low skew and balanced latency. • Collaboration & Process: Worked closely with RTL, design verification, and backend teams, owning the hand-off from logical to physical implementation while enforcing DRC and LVS constraints.

Stackforce AI infers this person is a VLSI engineer specializing in ASIC design and physical design methodologies.

Location: Dhanbad, Jharkhand, India

Experience: 4 yrs 3 mos