Aug 2023 – May 2025 · 1 yr 9 mos · Bengaluru, Karnataka, India · On-site

• 1. Involved in R&D and skilled-manpower training on Analog and Mixed Signal Design as part of the ChipIN team managing the Chip to Startup (C2S) Programme of the Ministry of Electronics and Information Technology, Govt. of India.
• 2. Conducted in-depth device characterization for SCL 180nm PDK across PVT corners.
• 3. Designed Ring Oscillators, RNG, BGR, High-gain Op-amp and In-amp blocks.
• 4. Detailed quantitative modelling of all blocks followed by Schematic to Hard-Macro full custom design using SCL 180nm PDK.
• 5. Complete Post-Layout Verification and Testing done including PVT and Monte Carlo simulations.
• 6. Tools used: Cadence Virtuoso, Siemens Calibre nmPlatform Physical Verification Suite.

Jul 2022 – Jul 2023 · 1 yr · Bengaluru, Karnataka, India · On-site

• Honorable Mention Paper at the 27th International Symposium on VLSI Design and Test (VDAT-2023) for paper titled - "A 0.076-mW 9.8-ENOB 1-MS/s SAR ADC using novel R-C hybrid DAC"
• 1. Worked in R&D with the Analog and Mixed Signal Design Team of the Secure Hardware and VLSI Design Group.
• 2. Designed Bootstrapped Sampling Switch, Dynamic Double-Tail Comparator, DAC and SAR ADC blocks.
• 3. Detailed quantitative modelling of all blocks followed by Schematic to Hard-Macro full custom design using SCL 180nm PDK.
• 4. Complete Post-Layout Verification and Testing done including PVT and Monte Carlo simulations.
• 5. Tools used: Cadence Virtuoso, Calibre nmPlatform Physical Verification Suite.

Jul 2021 – May 2022 · 10 mos · On-site

• 1. Successfully generated different tonic and bursting spiking patterns with the circuit and achieved biologically plausible (~1ms) time constants for regular spiking and spike frequency adaptation.
• 2. Achieved > 80% reduction in energy per spike by using a novel low power comparator and an input current < 2nA.
• 3. The novel neuron was implemented as a singe neuron encoder and a low frequency biphasic encoder. Both designs achieved similar accuracy of ~60dB as existing models with a reduced transistor count and over 50% decrease in power consumption.
• 4. Worked on the schematic-to-layout design, in 45nm CMOS technology (GPDK045). The design and post layout verification was done in the Cadence Virtuoso environment and Assura Physical Verification tools.

Apr 2021 – Nov 2021 · 7 mos · On-site

• 1. Worked on the custom mixed-signal layout of a Composite Phase Frequency Detector Based Low Power Low Noise Fast Locking PLL sponsored by the SMDP-C2SD Programme granted by the Ministry of Electronics and Information Technology, Govt. of India.
• 2. Phase Locked Loop (PLL)
• 3. Schematic to GDS full custom design using SCL 180nm PDK and post-layout analysis.
• 4. Deep N-Well and separate power-lines used to isolate analog and digital blocks in layout.
• 5. Tools used: Cadence Virtuoso, Calibre nmPlatform Physical Verification Suite.
• 6. PLL ASIC fabricated at SCL using 4-metal 180nm technology.

May 2019 – Jun 2019 · 1 mo · Chennai, Tamil Nadu, India · On-site

• 1. Designed an intelligent LPG cylinder stand, keeping in mind the standalone cylinders still used in Indian markets, that sends an app based alert to users to refill the cylinder when the gas level goes too low.
• 2. Worked on the PCB design for an ATMega328P microprocessor based circuit in DesignSpark environment, with the aim to reduce power consumption and increase battery life.
• 3. Ensured the design adhered to the EMIC standards for domestic electronic appliances and also tried PCB design techniques to reduce cross-talk and noise in the system.
• 4. Implemented an Arduino code for the system to accurately measure and notify the real time system parameters.
• 5. Completed Summer Sandbox 2019 at MaDeIT Innovation Foundation developing the product idea.