Pranav Vyas

Director of Engineering

India22 yrs experience
Highly Stable

Key Highlights

  • 20 years of experience in VLSI/ASIC physical design.
  • Expert in managing large teams and complex projects.
  • Alumnus of IIM Ahmedabad, enhancing management skills.
Stackforce AI infers this person is a Semiconductor VLSI/ASIC expert with strong management capabilities.

Contact

Skills

Other Skills

Physical DesignASICScriptingAwkTCLTiming ClosureCongestion ControlPrimetimeModelSimPlace & RouteTimingPerlApplication-Specific Integrated Circuits (ASIC)

About

Hi, I’m Pranav. With over 20yrs of experience in Semiconductor VLSI/ASIC physical design, I enjoy a blend of technical hands-on as well as management experience. Started a career as Individual Contributor and worked in Bay area USA as consultant and gained global working exposure alongside some of the talented engineers from across the world. Later, I have grown to handle a sizable team, key customer accounts, and project execution to deliver with the team of excellent engineers. Most of the key projects that I contributed are large, multi-million instances, high performance complex SoCs in Networking and Graphics domain that taped out on very cutting-edge lower tech nodes as low as 7nm and below. I am well versed with standard EDA tools from Synopsys and Candence for place and route as well as RC Extraction, STA/Timing and Physical Verification signoff till tapeout. I honed my management skills by completing a blended management program for senior professionals and became an Alumnus of prestigious IIM Ahmedabad in 2023. Domain: Networking SoC, Graphics SoCs Work profile: Place and Route (PNR), Netlist 2 gds flows, scripting/automation, flow/methodology EDA Tools: Synopsys (ICC2, StarRC, IC Validator), Cadence-Innovus, Mentor’s Calibre

Experience

22 yrs
Total Experience
4 yrs 6 mos
Average Tenure
9 mos
Current Experience

Verifast technologies

Director-ASIC Physical Design

Sep 2025Present · 9 mos

Einfochips (an arrow company)

3 roles

Associate Director – ASIC Physical Design

Promoted

Apr 2022Sep 2025 · 3 yrs 5 mos

Technical Manager

Oct 2017Sep 2025 · 7 yrs 11 mos

Sr. Technical Lead

Jan 2013Sep 2025 · 12 yrs 8 mos

Cadence design systems

Member of Consulting Staff

Jan 2012Jan 2013 · 1 yr

Amd

Senior ASIC Design Engineer

Feb 2010May 2012 · 2 yrs 3 mos

Cswitch inc

Consultant Physical Design Engineer

Jan 2006Jan 2007 · 1 yr · Santa Clara CA USA

Einfochips

ASIC Engineer

Jun 2004Feb 2010 · 5 yrs 8 mos

Education

Indian Institute of Management Ahmedabad

Nov 2022Oct 2023

Calorex Institute Of Technology

PG Diploma in VLSI designs

Jan 2000Jan 2000

University

B.E — Instrumentation and Control

Jan 1995Jan 1999

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