P

Praveen kumar H.V

Software Engineer

Bengaluru, Karnataka, India13 yrs 1 mo experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in Analog Layout Design across multiple technology nodes.
Experience with top semiconductor companies like AMD and Texas Instruments.
Proficient in Mixed Signal and Physical Design methodologies.

Stackforce AI infers this person is a skilled Analog Layout Designer in the semiconductor industry.

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Skills

Core Skills

Analog Circuit DesignPhysical DesignMixed Signal

Other Skills

Analog Layout DesignCadence VirtuosoClock treeLoop filterBias circuitsOperational amplifiersLevel shiftersRegulatorsClock buffersBand gap referencePower switchesSecondary ESD circuitsTop level routingsMemory layout DesignMixed Signal Physical Design

About

Experienced Analog Layout Designer with experience in Top clients like AMD, ADI, TI and Global Foundries. Having experience from 180nm to recent 7nm finfet. Worked on ADC, DAC, Bandgap, Clock tree, clock buffers, level shifters,opamps, bias circuits, current mirrors, LDO's, regulators, etc.,

Experience

13 yrs 1 mo

Total Experience

2 yrs 4 mos

Average Tenure

7 yrs 10 mos

Current Experience

Texas instruments

Layout Designer

Aug 2018 – Present · 7 yrs 10 mos · bangalore

Physical DesignAnalog Layout DesignCadence VirtuosoAnalog Circuit Design

Globalfoundries

Contract layout designer

Oct 2017 – Aug 2018 · 10 mos · bangalore

Texas instruments

Contract Layout Designer

Jan 2015 – Jul 2017 · 2 yrs 6 mos · Bengaluru Area, India

>Clock tree
>Loop filter
>Peak detector
>Bias circuits
>Operational amplifiers
>Level shifters
>Regulators
>Clock buffers

Clock treeLoop filterBias circuitsOperational amplifiersLevel shiftersRegulators+3

Analog devices

Contract Layout Designer

Mar 2014 – Dec 2014 · 9 mos · Bengaluru Area, India

Analog Layout Design
>>Band gap reference
>>Level Shifters
>>Power switches
>>Secondary ESD circuits
>>Top level routings.

Analog Layout DesignBand gap referenceLevel ShiftersPower switchesSecondary ESD circuitsTop level routings+2

Amd

Contract Layout Designer

Aug 2013 – Jan 2014 · 5 mos · Bengaluru Area, India

Memory layout Design

Memory layout Design

Sankalp semiconductor inc

Design Engineer

May 2013 – Jul 2017 · 4 yrs 2 mos

.

Eklakshya vlsi r &d centre

MSPD layout designer Trainee

Oct 2012 – Jan 2013 · 3 mos · Hubli Area, India

Training on "Mixed Signal Physical Design" domain includes
>CMOS VLSI
>Standard cell layout design
>Analog layout design
>Shell scripting
>Skill coding
>project- "Phase Locked Loop (PLL)"

Mixed Signal Physical DesignCMOS VLSIStandard cell layout designAnalog layout designShell scriptingSkill coding+2

Education

KLE Society's College of Engineering and Technology Belgaum

Master of Technology (MTech) — VLSI Design and Embedded system

Jan 2010 – Jan 2012

University B.D.T college of engineering,Davangere

Bachelor of Engineering (B.E.) — Electronics and Communications Engineering

Jan 2006 – Jan 2010

SJVP PU College Harihar

Pre University — Science

Jan 2004 – Jan 2006

St Mary's convent school, Harihar

School

Jan 1994 – Jan 2004

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