Praveen Narendranath

Software Engineer

Bengaluru, Karnataka, India17 yrs 2 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Proven expertise in modem implementation and power optimization.
  • Strong background in circuit and physical design.
  • Extensive experience in custom IP design from RTL to GDS.
Stackforce AI infers this person is a Principal Engineer in the wireless industry, specializing in circuit and physical design.

Contact

LinkedIn

Skills

Core Skills

Circuit DesignPhysical Design

Other Skills

Modem ImplementationPowerModem DesignImplementationRTL DesignSynthesisFloorplanPlace and RouteTiming ClosureCustom Cell Library DesignSemi custom and full custom IP designsStandard Cell Library DesignCharacterizationAutomationLogic Design

About

Experienced Principal Engineer with a demonstrated history of working in the wireless industry. Strong engineering professional skilled in Circuit design, Implementation, Low power and Physical Design.

Experience

17 yrs 2 mos
Total Experience
8 yrs 7 mos
Average Tenure
12 yrs 11 mos
Current Experience

Qualcomm

5 roles

Principal Engineer/Manager

Promoted

Nov 2024 – Present · 1 yr 7 mos

  • Modem Implementation and Power
Modem ImplementationPowerCircuit DesignPhysical Design

Senior Staff Engineer/Manager

Promoted

Oct 2018 – Nov 2024 · 6 yrs 1 mo

  • Modem Implementation and Power.
Modem ImplementationPowerCircuit DesignPhysical Design

Staff Engineer

Jun 2016 – Sep 2018 · 2 yrs 3 mos

  • Modem Design and Implementation.
Modem DesignImplementationCircuit DesignPhysical Design

Staff Engineer

Apr 2015 – May 2016 · 1 yr 1 mo

  • Semi custom and full custom IP designs from RTL to GDS.
  • (RTL/Circuit Design/Synthesis/Floorplan/Place and Route/Timing Closure.)
RTL DesignCircuit DesignSynthesisFloorplanPlace and RouteTiming Closure+1

Senior Design Engineer

May 2013 – Apr 2015 · 1 yr 11 mos

  • Custom Cell Library Design.. Semi custom and full custom IP designs from RTL to GDS.
Custom Cell Library DesignSemi custom and full custom IP designsCircuit DesignPhysical Design

Intel

Component Design Engineer

Feb 2009 – May 2013 · 4 yrs 3 mos · San Francisco Bay Area

  • Standard Cell Library Design, Characterization & automation
Standard Cell Library DesignCharacterizationAutomationCircuit DesignPhysical Design

Education

University of Southern California

MS — Electrical Engineering (VLSI)

Jan 2007 – Jan 2008

Anna University Chennai

Bachelor of Engineering (B.E.) — Electrical and Electronics Engineering

Jan 2003 – Jan 2007

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