Pravith R

Software Engineer

Bengaluru, Karnataka, India7 yrs 9 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

7 years of experience in GPU design and verification.
Expert in performance verification and test case development.
Strong foundation in shader architecture and performance monitoring.

Stackforce AI infers this person is a Semiconductor Verification Engineer with expertise in GPU performance and design.

Contact

Skills

Core Skills

Performance VerificationDesign Verification

Other Skills

C++Compute shader programmingSystemVerilogCache CoherencyUVMPerlCode CoverageFunctional Coveragex86 AssemblyTest Plan developmentGraphics Processing Unit

About

Result-driven professional with 7 years of comprehensive experience in both Design and Performance Verification of GPUs. Expertise spans Functional and Performance Verification, test case development using Assembly languages (x86, Compute SP3), and scripting with Perl and Python. Possess a strong foundation in Shader Architecture, including GC-level Performance Verification, Single and Multi-threaded Pipelines, Thread Management Units, and Performance Monitoring Units. Highly motivated to contribute to the Performance Verification of next-generation Graphics Pipelines. You can connect to me at : pravithgr@gmail.com

Experience

7 yrs 9 mos

Total Experience

3 yrs 10 mos

Average Tenure

4 yrs 10 mos

Current Experience

Amd

2 roles

Senior Silicon Design Engineer

May 2023 – Present · 3 yrs · Hybrid

I do Performance analysis and validation of next generation AI & HPC GPUs.

C++Compute shader programmingPerformance Verification

Silicon Design Engineer 2

Jun 2021 – Apr 2023 · 1 yr 10 mos · Hybrid

Role : Performance Verification
Was a part of Graphics Core Performance Verification team, Owned and executed Shader sub-system perf tests.

SystemVerilogCache CoherencyPerformance Verification

Wipro limited

Verification Engineer

Jun 2018 – May 2021 · 2 yrs 11 mos · Bengaluru, Karnataka, India · On-site

Role : Design Verification
Collaborated as a key member of the Core-level Verification team, developing comprehensive test plans across Sub-system, Core, and SoC levels for new Graph Processor features.
Designed and implemented ASM test cases from scratch, focusing on multiple new feature scenarios primarily targeting the Thread Management Unit.
Automated the generation of Extended Path Clearing ASM test cases using Perl scripts, successfully identifying design bugs through these tests.
Debugged failing ASM test cases during regression testing caused by various issues; reported over 90 RTL bugs and worked closely with designers to resolve both RTL and test-related problems. Verified design fixes by creating more extensive test scenarios.
Streamlined verification of Hardware Performance Counters by developing a reference model within the testbench, along with tracker files and functional coverage points for each counter.
Achieved 100% code and functional coverage for the Thread Management Unit, Performance Monitoring Unit, and Data Cache Coherency block.

UVMSystemVerilogDesign Verification