Prince Kushwaha — Product Engineer

I am a DFT (Design for Testability) Engineer specializing in Scan, ATPG, and MBIST implementation for complex SoC designs. Currently working at Tecquire Solutions Pvt. Ltd., I focus on building robust test architectures and ensuring high-quality silicon validation at both core and chip levels. My expertise includes scan insertion (hierarchical and full-chip), OCC integration, compression logic, and wrapper implementation, along with ATPG generation, pattern validation, and formal verification using industry-standard Synopsys tools. I have hands-on experience with MBIST using STAR Memory System, including SMS pattern generation, simulation setup (RTL/GLS/SDF), and debugging timing and functional issues. I also have a strong understanding of JTAG architecture, TAP controller FSM, and boundary scan validation. From a technical standpoint, I work extensively with: Tools: Synopsys DC, TetraMax, Formality, Verdi, VCS, Silicon Debugger Languages: Perl, Tcl, Bash, C/C++ Domains: DFT Architecture, Scan, ATPG, MBIST, JTAG I enjoy solving complex debugging challenges, automating workflows, and optimizing test methodologies for scalable designs. I am open to opportunities where I can contribute to advanced VLSI/SoC design projects, particularly in organizations focused on high-performance and low-power semiconductor solutions.

Stackforce AI infers this person is a Semiconductor DFT Engineer with expertise in test architecture and validation.

Location: Noida, Uttar Pradesh, India

Experience: 2 yrs 10 mos