Raghavendra Padmanabha

Director of Engineering

Bengaluru, Karnataka, India25 yrs 11 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Senior Director with extensive ASIC experience
Proficient in multiple hardware description languages
Strong background in functional verification and embedded systems

Stackforce AI infers this person is a seasoned leader in ASIC design and verification within the semiconductor industry.

Contact

Skills

Core Skills

Functional VerificationAsic

Other Skills

SystemVerilogC++VerilogVHDLPerlEmbedded SystemsDebuggingRTL design

Experience

25 yrs 11 mos

Total Experience

3 yrs 8 mos

Average Tenure

4 yrs 5 mos

Current Experience

Sifive

Senior Director

Jan 2022 – Present · 4 yrs 5 mos · Bangalore Urban, Karnataka, India

Functional VerificationSystemVerilogC++VerilogVHDLPerl+4

Intel corporation

2 roles

Director Of Engineering

Promoted

Apr 2021 – Jan 2022 · 9 mos

SoC CPU Validation Lead

Oct 2016 – Apr 2021 · 4 yrs 6 mos

Qualcomm

Sr Staff Manager

Apr 2016 – Sep 2016 · 5 mos · Bengaluru Area, India

Samsung research india

Senior Chief Engineer

Feb 2013 – Apr 2016 · 3 yrs 2 mos · Bengaluru Area, India

Amd

Senior Member Technical Staff

Aug 2010 – Feb 2013 · 2 yrs 6 mos

Freescale

Sr. Verification Engineer

May 2005 – Aug 2010 · 5 yrs 3 mos

Ibm corporation

PowerPC Verification Engineer

Jun 2000 – May 2005 · 4 yrs 11 mos

Education

Bangalore University

BE — Telecommunication

Jan 1995 – Jan 1999

Stackforce found 100+ more professionals with Functional Verification & Asic

Explore similar profiles based on matching skills and experience

HARISH RAO L

Physical Design Engineer (On contract)

at Intel

Hyderabad, India2 yrs 10 mos exp

Physical Design EngineerDigital Hardware DesignSynthesis Design

Suman Sekhar Jana

Senior Low Power Verification Engineer

at NVIDIA

Kolkata, India6 yrs 11 mos exp

DDRPHY VerificationSystem Verilog

Shivanshu Trivedi

Physical Design Engineer

at NVIDIA

Lakhimpur, India7 yrs 10 mos exp

Physical DesignStatic Timing Analysis

Ankit Jindal

Engineering Manager

at NVIDIA

Bengaluru, India9 yrs 1 mo exp

Machine LearningGenerative AIPost-Silicon ValidationSolar Energy

Anandu Narayanan

Senior Verification Engineer

at NVIDIA

Tiruvalla, India6 yrs 10 mos exp

Universal Verification Methodology (UVM)

Swathi Narala

Senior Staff Engineer

at Qualcomm

Bengaluru, India13 yrs 11 mos exp

Gayathri R

Prinipal Application Engineer

at Cadence Design Systems

Bengaluru, India10 yrs 11 mos exp

VLSIPhysical DesignLayout VerificationBlock Level Implementation

Hardik Jirawala

Principle Design Engineer

at Cadence

Bengaluru, India11 yrs 11 mos exp

Physical DesignVLSIStatic Timing AnalysisSoC DesignClock Tree Synthesis