Raju . — Software Engineer
Experience on Ring based PLL (Architecture of PLL & Circuit Design of PFD, Charge Pump, LPF, Ring Oscillator & Local Oscillator Blocks) Worked on fdsoi 22nm(gf ) ,65nm, 180nm CMOS in Cadence Virtuoso. Course- Analog IC design, Digital IC design, Hardware Design Methodlogy, Digital System Design, MOS device Physics , RF Microelectronics, Computer Organization and Architecture. Skilled/Interest - #CMOS based amplifiers, #STA, #PLL #Analog IC Designing, #Digital IC Designing and #verification, #ASIC Design #Static Timing Analysis (STA) Tools and Languages: Simulation Tool: PSpice, LT-Spice,Cadence Virtuoso HDL: Verilog (Xilinx Vivado) NEGF & DFT Tool:Synopsys QuantumATK Programming Skills: Verilog, MATLAB, Basic C,Java. Linux
Stackforce AI infers this person is a Microelectronics expert with a focus on Analog and Mixed-Signal IC Design.
Experience: 2 yrs 11 mos
Skills
- Analog Circuit Design
- Mixed-signal Ic Design
- Digital Electronics
- Electrical Engineering
Career Highlights
- Expert in Analog Circuit Design and Mixed-Signal IC Design.
- Hands-on experience with advanced PVT analysis and reliability verification.
- Strong foundation in VLSI design and digital electronics.
Work Experience
Sasken Technologies Limited
Analog Circuit Design Engineer (2 yrs 3 mos)
SingularityAIX
Jr .Analog Circuit Design Engineer (8 mos)
Indraprastha Institute of Information Technology, Delhi
IIIT DELHI VLSI SUMMER TRAINING (2 mos)
Indian Institute Of Information Technology
Teaching Assistant (1 yr 5 mos)
B.P Mandal Coollege Of Engineering Madhepura Bihar
Internship Trainee (8 mos)
Indian Railways
East Central railway (1 mo)
Education
Master of Technology at Indian Institute Of Information Technology Allahabad
B.tech at Institute Of Engineering and Management
Higher secondary at Thakur prasad college patna (Bihar School Education board)
JEE Advance preparation at FIITJEE
at Jawahar Navodaya Vidyalaya - JNV