Rakesh Karmakar

Software Engineer

Austin, Texas, United States8 yrs 5 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expertise in VLSI and Physical Design.
Strong foundation in Electrical and Electronics Engineering.
Proficient in multiple programming languages and design tools.

Stackforce AI infers this person is a VLSI Engineer with strong capabilities in physical design and semiconductor technologies.

Contact

Skills

Core Skills

VlsiPhysical DesignElectrical Engineering14 Nm Finfet Technology

Other Skills

CC++PythonCadence VirtuosoCALIBRESynopsys toolsC/C++PERLCadence InnovusSystemVerilogMatlab-SimulinkMultisimAutoCadHspice8085

About

Rakesh is an Engineer at Apple. He completed his Master's in Electrical and Computer Engineering at the University of Minnesota- Twin Cities. He graduated in December, 2018. His professional goal is to learn new things and garner knowledge on the latest technologies of the Electrical and Electronics Engineering field through fundamental concepts and research. His main interests lie in the fields of VLSI. He is open to both Back End and Front End fields of VLSI. Skillset: 1. Programming and Scripting Languages: C/C++, PERL, Python. 2. Tools: Cadence (Virtuoso), Cadence (Innovus), Calibre (DRC, LVS, PEX, RVE), Synopsys (HSPICE, CSCOPE, VCS, DVE), SystemVerilog, Matlab-Simulink, Multisim, AutoCad, Hspice. 3. Assembly Level Programming: 8085, 8086 and 8051 4. Raster and Vector Graphics editing: Adobe Photoshop, Corel Paintshop, Gimp. 5. Has exposure to 7nm , 14nm FINFET Technology as well as 45nm Technology. He completed his Bachelor of Technology degree in Electrical Engineering from the National Institute of Technology, Durgapur (NIT, Durgapur), India with a GPA of 8.81 out of 10. His rank was 7th in a class of around 94 students. After Bachelors, he worked full-time at Larsen & Toubro Construction(L&T) as a Graduate Engineer Trainee (from 2015-2016) under the Power Transmission and Distribution Department. His project, ‘RGGVY Works, Aligarh’, Uttar Pradesh, India.

Experience

8 yrs 5 mos

Total Experience

2 yrs 9 mos

Average Tenure

7 yrs 4 mos

Current Experience

Apple

Engineer

Feb 2019 – Present · 7 yrs 4 mos · Austin, Texas Area

CC++PythonCadence VirtuosoCALIBRESynopsys tools+2

Globalfoundries

Intern

May 2018 – Aug 2018 · 3 mos · Rochester, Minnesota Area

Roles: Physical Design Flow (Floor-planning, placement, routing, timing, congestion optimization etc.) on several designs.
Technology: 14 nm FinFET
Tools: Cadence: Innovus.

Physical Design FlowFloor-planningPlacementRoutingTimingCongestion optimization+3

University of minnesota-twin cities

Graduate Student at the University of Minnesota, Twin Cities

Sep 2017 – Dec 2018 · 1 yr 3 mos · Greater Minneapolis-St. Paul Area

His professional goal is to learn new things and garner knowledge on the latest technologies of the Electrical and Electronics Engineering field through fundamental concepts and research.
His main interests lie in the fields of VLSI. He is open to both Back End and Front-End fields of VLSI.
Skillset:
1. Programming and Scripting Languages: C/C++, PERL, Python.
2. Tools: Cadence (Virtuoso), Cadence (Innovus), Calibre (DRC, LVS, PEX, RVE), Synopsys (HSPICE, CSCOPE, VCS, DVE), SystemVerilog, Matlab-Simulink, Multisim, AutoCad, Hspice.
3. Assembly Level Programming: 8085, 8086 and 8051
4. Raster and Vector Graphics editing: Adobe Photoshop, Corel Paintshop, Gimp.
5. Has exposure to 7nm , 14nm FINFET Technology as well as 45nm Technology.
He completed his Bachelor of Technology degree in Electrical Engineering from the National Institute of Technology, Durgapur (NIT, Durgapur), India with a GPA of 8.81 out of 10. His rank was 7th in a class of around 94 students.
After Bachelors, he worked full-time at Larsen & Toubro Construction(L&T) as a Graduate Engineer Trainee (from 2015-2016) under the Power Transmission and Distribution Department. His project, ‘RGGVY Works, Aligarh’, Uttar Pradesh, India.