Aug 2022 – Nov 2023 · 1 yr 3 mos · Bengaluru, Karnataka, India · On-site

• Built a team of 30 people, deployed Cadence, and Synopsys tool flows from RTL to GDSII.
• Managed physical implementation, signoff & tapeout activities for a phased antenna array ASIC using channel-based floorplan with 800 memory and 100 analog macro instances. Target technology 28nm HPC+, 1P9LM+ALRDL with BGA package. Used Synopsys Fusion Compiler for physical implementation and Primetime/ICV and Ansys Redhawk for Signoff.
• Training and building expertise specific to customer deliverables.

Aug 2018 – Sep 2022 · 4 yrs 1 mo · Bengaluru, Karnataka, India

• Worked on 3rd generation Xeon Server SoC named ICELAKE-D LCC. As SD Manager, responsible for TR-Exit, SD0p5 and SD0p8 closure. Managed deliverables to FCL (physical signoff), FCT (timing signoff) teams.
• Delivered multiple SoCs tapeout in TSMC 16nm technology, while managing SD team at CHD (Connected Home Division).
• Delivered subsystems while working with graphics IP group, AXG.As part of design signoff responsibility, managed all the verification and paranoia checklists across the physical implementation cycles and executed milestone marking for graphics SoCs/sub-systems for each milestone.
• ICELAKE-D LCC, Intel 10nm
• Wifi 6 chip – wave600 , 700 MHz, TSMC 16nm
• ABB test chip – AFE, 900 MHz, TSMC 16nm
• Falcon - 6.6M gate count, 800 MHz, TSMC 28nm
• Multiple Sub-Systems in Ponte Vecchio and Rialto bridge GPUs, Intel 10nm

Apr 2015 – Aug 2018 · 3 yrs 4 mos

• Over a period of 12 years, worked in Smart TV, internal physical design services and networking divisions.
• Worked on several products from digital TV, wireless, networking to storage.
• Was responsible for RTL to GDSII activities out of Marvell India, Bangalore and taped out multiple SoCs.
• Handled fullchip gds delivery including package and system design interactions.
• Had exposure to integrate multiple PHYs like DDRPHY, SATA, HDMI, SERDES.
• Delivered one of the biggest chips in Marvell in the year 2015 with 22 million place-able instances consisting of 8 multiple instantiated modules on a die size of 400+ mm2 with 9000+ bumps FCBGA package. Built Fullchip hierarchical and flat STA signoff methodology. Target technology TSMC 28nm HPM.
• Exposure to multiple packaging designs, QFP, Wire-bond and FCBGA.
• Worked with cross-site teams in Singapore, San Jose, and Israel.

Apr 2011 – Mar 2015 · 3 yrs 11 mos

Apr 2010 – Apr 2011 · 1 yr

May 2006 – Apr 2010 · 3 yrs 11 mos

Jun 2004 – May 2006 · 1 yr 11 mos · Bengaluru, Karnataka, India

• Taped out 4 display processors with gate counts varying from 4 million to 7 million.
• Flat physical implementation of 4 million-gate, memory intensive design. Handled from synthesized net list to GDSII.
• Tools: Astro
• Involved in hierarchical physical implementation of 7 million-gate memory and analog macro intensive design. Partly responsible for hierarchical physical design flow setup. Involved in clock network analysis, clock tree synthesis and inter clock skew balancing in functional and test modes with single test clock domain. Involved in the planning of routing channels and hierarchical PG ring construction.
• Tools: Astro
• Developed bond pad placer utility and there by quickened data preparation for build sheet generation.
• Languages: Unix Shell programming, Scheme and PERL

Aug 2000 – Jun 2004 · 3 yrs 10 mos · Bengaluru, Karnataka, India

• Taped out 6 display processors in 0.18 um technology with gate counts varying from 800k to 1.5 million. Responsible for complete physical implementation of 3 display processors. Responsible for physical verification, power grid analysis and signal integrity checks on other 3 display processors.
• Tools: Apollo
• Physical implementation of 500k-gate core DTV blocks in 0.13 um technology using multi-Vth libraries.
• Tools: PC, Astro

Mar 1999 – Aug 2000 · 1 yr 5 mos · Bengaluru, Karnataka, India

• Worked on i-flex solutions (now Oracle) flagship banking product FLEXCUBE. Ported funds transfer module from Oracle to VC++.