Sampath V. — Software Engineer
Stackforce AI infers this person is a skilled ASIC Verification Engineer with a focus on digital design and verification methodologies.
Location: Bengaluru, Karnataka, India
Experience: 6 yrs 4 mos
Skills
- Universal Verification Methodology (uvm)
- System Verilog
- Unipro
Career Highlights
- Over 5 years of experience in ASIC RTL Verification.
- Proficient in Universal Verification Methodology (UVM) and System Verilog.
- Strong background in digital circuit design and RTL coding.
Work Experience
Synopsys Inc
ASIC Digital Design Staff Engineer (1 yr 4 mos)
ASIC Digital Design Engr, 2 (2 yrs 10 mos)
ASIC Digital Design Engr, 1 (1 yr 6 mos)
Technical Engineer (11 mos)
Dolcera
Patent research and analysis (8 mos)
Education
Bachelor of Engineering at Chaitanya Bharathi Institute Of Technology
BOIE at Sri Chaitanya Raman Bhavan 1& 2
SSC at Dr.KKR Gowtham Concept School
