Apr 2021 – Jul 2021 · 3 mos

May 2018 – Apr 2021 · 2 yrs 11 mos

• Specialties:
•  Designed and enhanced various modules/sub modules for Streaming Processor IP.
•  Good design exposure on parallel processor, and shared memory load/store block.
•  Design and verification of last level cache and crossbar switch for a parallel processor.
•  ASIC/ FPGA-based Digital Design & Verification.
•  Algorithm to Architecture.
•  RTL Coding and Synthesis.
•  RTL performance, power, and area Optimization
•  Clock Domain crossing analysis for module and SoC
•  Design and development of video DMA block.
•  Working experience on Palladium.
•  Failure mode analysis includes fault in the safety mechanism and to determine diagnostic
• coverage.
•  Part of ISO-26262 working group member and responsible to meet IP for ASIL-x capable.

Apr 2014 – Mar 2016 · 1 yr 11 mos

• Responsible for aerospace design and application support, including developing complex SOC design for mobile handsets. Responsibilities included:
• Design and development of SRAM controller in Verilog.
• Design and development of BLDC Motor controller using PID algorithm in Verilog.
• Design and Implemented of Multi-Function Timer and PWM module in Verilog RTL.
• ARIN-429 communication protocol development for aero space application.
• FPGA proto typing in Xilinx Zynq Board.
• Writing constraints and executing RC based synthesis flow.
• Integration of multimedia subsystem to SOC environment and Timing closure of SOC in kintex-7 FPGA.
• CDC and lint at full chip level.
• Validation support using Xilinx analyser by creating Tcl based e-flow.
• Verilog System level Modelling
• Tools supported include Cadence HAL, CDC and irun.

Feb 2012 – Apr 2014 · 2 yrs 2 mos · Greater Hyderabad Area

• Responsible for aerospace design and application support including development of communication protocol design. Responsibilities included:
• Design and development of DDR controller.
• CAN RTL design for aerospace application.
• Video data Processing.
• FPGA proto typing in vivado Board.
• CDC and lint at IP level.
• Timing analysis and creating constrains.
• Validation support using Xilinx analyser by creating Tcl based e-flow.
• Primary activities include implementing DDR Controller and CAN RTL design using Verilog.

Jun 2011 – Sep 2012 · 1 yr 3 mos · Pune/Pimpri-Chinchwad Area

• Responsible for design and development application for SOC for mobile handsets. Role involves:
• Designing and Development and integration of I2s, TDM and TXDR Boost controller.
• Development of varies communication protocol design.
• Handled project execution; including schedule preparation, task distribution, micro-architecture design and code reviews, project monitoring, team management.
• Spyglass Linting and Code coverage support for verification team.
• CDC and lint at IP level.
• Timing analysis and creating constrains.
• SOC prototyping in Xilinx FPGA.
• Primary activities include implementing RTL design using Verilog and timing analysis.

Dec 2008 – Mar 2011 · 2 yrs 3 mos · Mysore

Mar 2004 – Dec 2008 · 4 yrs 9 mos

• Responsible for design and development for Satellite Application for ISRO.
• Role involves:
• Designing and Development of Image data (Satellite) Acquisition systems.
• Design and development of frame synchronization Module for varies satellite.
• development of SDRAM communication protocol.
• Designing of motor control systems for medical application.
• CDC and lint at IP level.
• Timing analysis and creating constrains.
• Primary activities include implementing RTL design using Verilog and timing analysis.