Apr 2019 – Apr 2020 · 1 yr · Hyderabad Area, India

Sep 2016 – Mar 2019 · 2 yrs 6 mos · Hyderabad Area, India

• Full Chip floorplanning (both top to bottom bottom to top channelless )
• Pin planning for channel less design
• Bump Planning
• Block Level Implementaton
• FullChip Implemenation : 3 Chip Top
• Block Level Implementation : 6 blocks

Apr 2014 – Aug 2016 · 2 yrs 4 mos · Hyderābād Area, India

• PnR flow with Timing closure with DRC cleaned

Jul 2013 – Mar 2014 · 8 mos · Mumbai Area, India

• RTL Coding
• Test Benches
• Schematic Design
• Board Bringup
• STA

Nov 2012 – May 2013 · 6 mos · hyderabad

• VLSI Fundamentals, CMOS Basics, Digital Design, Floor Planning, Power Planning, Placement and Routing, clock tree synthesis, static timing analysis, cross talk analysis, IR Drop Analysis and Physical Verification
• Experienced in physical design of 130nm and 90nm technologies using Cadence tools
•  Cadence SOC Encounter – Floor Planning, Place & Route, and clock tree synthesis
•  Encounter Timing System – Static Timing Analysis and Crosstalk Analysis
•  RTL Compiler- Logic Synthesis
•  Assura – Physical Verification

Aug 2011 – Oct 2012 · 1 yr 2 mos · Navi Mumbai

• Roles and Responsibilities:
• Designing Video Multiplexer using Verilog.
• Designing of hardware module for FPGA Design.
• Prototyping Video Multiplexer through PCIe
• Board BRINGUP
• Design Analysis