Shashwat Kaushik

Product Engineer

Delhi, India8 yrs 9 mos experience

Highly Stable

Key Highlights

Expert in Analog Design and VLSI.
Proven track record in designing complex circuits.
Strong background in power management systems.

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in Analog Circuits and VLSI.

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Skills

Core Skills

Analog CircuitsVery-large-scale Integration (vlsi)

Other Skills

Voltage RegulatorsPLL loop BandwidthDuty Cycle Correction circuitsADC designClock skew measurement circuitsHigh BandwidthNoise sensitivityMoM cap measurementRC time constant measurement8 bit SAR ADCR-C hybrid DACReference buffer designSettling time optimizationLDO structure improvementPMU architecture

Experience

8 yrs 9 mos

Total Experience

2 yrs 2 mos

Average Tenure

Current Experience

Cadence

Lead Design Engineer

Jul 2023 – Aug 2025 · 2 yrs 1 mo · Noida, Uttar Pradesh, India · On-site

SerDes is a complex system and need variety of Auxiliary blocks to make it work effectively.
1. I have designed the Voltage Regulators which power the VCO and the Clock Distribution circuits. Both of these blocks are noise sensitive which adds significant Jitter.
The regulator helps to cut off the supply jitter (high PSRR) and also should be of Ultra low noise and High Bandwidth. (Additional challenge was the HV tolerance circuits design)
2. PLL loop Bandwidth is crucial for overall stability and the noise performance of system. But loop Bandwidth is subject to Process variation which needs trimming and Its a multistep process to aet it correctly So I worked on designing a MoM cap measurement and RC time constant measurement circuits to ease the PLL loop Bandwidth trimming process.
3. Jitter propagation is common and less desirable at the TX or RX site. A local Duty Cycle Correction circuits is required. I have also worked on DCC.
4. For Testing the internal Voltage and current of several blocks we use Internal ADC . The requirements is less stringent in terms of accuracy.
So I also Worked on a 8 bit SAR ADC. The circuit was simplified from an Area perspective and we used R-C hybrid DAC and also removed the reference Buffer as the available timing was good enough for settling.
5. I have designed a Refrence buffer for 32 Time interleaved 7 bit asynchronous ADC used in PAM4 based PCIE. (Challenge was mainly the settling time within desired accuracy) and the good PSRR.
6. PAM4 based PCIE6 have stringent timing constraints so the sampling clock skew calibration with accuracy is the important factor. For that I have worked on the Clock skew measurement circuits. That uses 7 bit SAR ADC.

Voltage RegulatorsPLL loop BandwidthDuty Cycle Correction circuitsADC designClock skew measurement circuitsAnalog Circuits+1

Career break

Personal goal pursuit

Oct 2022 – Jun 2023 · 8 mos · Noida, Uttar Pradesh, India

Thought Explorer (अप्प दीपो भव :|)

Stmicroelectronics

2 roles

Technical Lead

Promoted

Nov 2020 – Sep 2022 · 1 yr 10 mos

I have improved the LDO structure (see patents), worked on complex PMU architecture which supports High voltage range using low voltage tolerant devices. Additionally worked upon Antenna Sensing structure (which supplies power to an active antenna), its complexity was mainly to support HV range.

LDO structure improvementPMU architectureAntenna Sensing structureVery-Large-Scale Integration (VLSI)

Sr. Design Engineer

Jun 2017 – Oct 2020 · 3 yrs 4 mos

Design and verification of various power management blocks( monitors, PoR, B-Gap, Regulators, Level shifters), High speed comparator, Glitch filter, process monitoring sensors.

Power management blocks designHigh speed comparatorGlitch filterProcess monitoring sensorsVery-Large-Scale Integration (VLSI)

Nxp semiconductors

Design Engineer

Jul 2016 – May 2017 · 10 mos · Noida Area, India

As an designer I was responsible for designing high speed SPI interface built for pressure sensor system.
Also I was managing power up sequence control of RF communication blocks.
I have also designed & made layout of Op-amps.

High speed SPI interfacePower up sequence controlOp-amps design and layoutAnalog Circuits

Stmicroelectronics

Trainee

Aug 2015 – Jun 2016 · 10 mos · Greater Noida

During that period, I was involved for bit-cell characterization used for low voltage adaptive memory subsystem implemented in 28-UTBB FDSOI. In this project adaptive body bias was used to get optimal performance of memory sub system across temperature and process variations. So, I contributed successfully, to find the relation among FoMs and variability in conjugation to body-bias voltage.
Furthermore, I was contributing on the project "weak bits detection methodology in SRAM array and the cost effective circuit setup for the testing", with my fellow colleagues. This project fetched us publication in reputed conference (SOCC,2016 held in USA).
With completion of internship, my take away is understanding of SRAM memory architecture, memory compiler, timing sequence for self timed memory, Monte-carlo, effect of temperature and process on the FoMs, Yield analysis, memory bit failure and its recovery using redundancy and ecc, multi-Vt design, low leakage and low power techniques.

Bit-cell characterizationWeak bits detection methodologyAdaptive body biasVery-Large-Scale Integration (VLSI)