Ashish Yadav

Software Engineer

India8 yrs 6 mos experience

Highly Stable

Key Highlights

Over 8 years of ASIC engineering experience
Expertise in low-power RTL design and verification
Proven track record in delivering power-efficient ASIC solutions

Stackforce AI infers this person is a Semiconductor Verification Engineer specializing in low-power ASIC design.

Contact

Skills

Core Skills

Rtl VerificationLow-power DesignUniversal Verification Methodology (uvm)Pcie

Other Skills

Application-Specific Integrated Circuits (ASIC)powersystem verilogC++Data StructuresDigital ElectronicsVery-Large-Scale Integration (VLSI)PythonCEmbedded SystemsModelSimAnalog CircuitsVerdiDveScripting

About

Experienced ASIC engineer with over 8 years of expertise in low-power RTL design, verification, and integration. Specialized in power management features, dynamic and static verification, and end-to-end development from architecture to post-silicon validation. Skilled in: -Developing SV-UVM-based verification environments and test plans -Power gating, retention, and clock gating verification techniques -UPF-based low-power verification and debugging at block, sub-system, and full-chip levels -Building in-house tools and checkers for power methodology enablement -Driving regression setups and collaborating across architecture, design, and validation teams With a proven track record in delivering power-efficient and robust ASIC solutions, I bring a systems-level perspective and a passion for solving complex verification challenges.

Experience

8 yrs 6 mos

Total Experience

2 yrs 6 mos

Average Tenure

9 mos

Current Experience

Amd

MTS Silicon Design Engineer

Jul 2025 – Present · 9 mos · Hyderabad, Telangana, India

Nvidia

ASIC Engineer

Feb 2021 – Jun 2025 · 4 yrs 4 mos · Bengaluru, Karnataka, India

Member of the Low Power Team for GPU & Tegra Chips :
● Working on the engine level power gating features in GPU’s
● RTL verification and working with architects for feature deployment
● Working with power methodology team to implement in-house
checkers and enable them in live projects
● Working with multiple teams for power estimation , latencies &
silicon bring up for power gating features.

RTL VerificationApplication-Specific Integrated Circuits (ASIC)Low-power Designpower

Qualcomm

Engineer

Feb 2019 – Jan 2021 · 1 yr 11 mos · Noida Area, India

Mainly working on Low Power and Functional verification at DDR Subsystem level.
Test and verification plan creation with project timeline for feature verification for Power Aware RTL verification.
Project specific environment architecture development.
Attained good understanding of power saving features along with the architecture scope for power management and saving logic.
Grasp over interpretation of UPF and standard cell usage.
SV-UVM based sequence creations for low power features and assertions based checker module development.
Regression setup creation and execution along with rigorous debugs across subsystem as well as SoC level.

RTL VerificationApplication-Specific Integrated Circuits (ASIC)Low-power Design