Sheetal Swaroop Burada

Product Engineer

Noida, Uttar Pradesh, India6 yrs 10 mos experience

Highly Stable

Key Highlights

Expert in Formal Verification methodologies.
Proficient in Jasper and related tools.
Strong background in Digital IC Design.

Stackforce AI infers this person is a Formal Verification Engineer with expertise in Digital IC Design.

Contact

Skills

Core Skills

Formal Verification

Other Skills

JasperVerilogSystemVerilogUniversal Verification Methodology (UVM)Automatic Test Pattern Generation (ATPG)DFTDigital IC DesignApplication-Specific Integrated Circuits (ASIC)RTL DesignRTL VerificationAssertion Based VerificationSystem Verilog Assertions

Experience

6 yrs 10 mos

Total Experience

2 yrs 11 mos

Average Tenure

1 yr

Current Experience

Synopsys inc

Staff Application Engineer

Jun 2025 – Present · 1 yr · Noida, Uttar Pradesh, India · On-site

Product Engineering - VC Formal

Formal VerificationJasper

Cadence design systems

2 roles

Lead Application Engineer

Jul 2023 – Jun 2025 · 1 yr 11 mos · Noida, Uttar Pradesh, India

Formal VerificationJasper

Senior Application Engineer

Dec 2021 – Jun 2023 · 1 yr 6 mos · Noida, Uttar Pradesh, India

Formal VerificationJasper

Nxp semiconductors

Design Engineer

Jul 2019 – Dec 2021 · 2 yrs 5 mos · Bengalore

Education

Dayalbagh Educational Institute

Bachelor of Engineering — Electrical and Electronics Engineering

Jan 2016 – Jan 2019

Dayalbagh Educational Institute

Diploma of Education — Electrical and Electronics Engineering

Jan 2013 – Jan 2016

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