May 2018 – Jan 2022 · 3 yrs 8 mos · Bengaluru, Karnataka, India

Mar 2017 – May 2018 · 1 yr 2 mos · India

• Working on STA and Synthesis.

Apr 2016 – Feb 2017 · 10 mos · Bengaluru Area, India

• Through Mindlance, I worked at Physical Design Engineer at Qualcomm.
• Main highlights of the work:
• 1. Floorpan
• 2. Place and Route
• 3. Signoff activities for the hard macro .
• The project I was involved in was in 10nm technology and was a hard macro in camera sub system.

Sep 2013 – Mar 2016 · 2 yrs 6 mos

• 1. Physical Design:
• (i) Responsibilities of Digital section of IP.
• (ii) Placement and routing of the design.
• (iii) Floorplan of design based on minimizing the area of the IP as well as meeting the timing constraints.
• (iv) Clock tree synthesis and analyzing of the CTS results.
• (v) If results of the CTS are met then proceeding to the post CTS stage and routing of the design.
• (vi) Cleaning of the DRC violations due to congestion.
• (vii) Checking of the DRC, LVS and DFM outside PnR tool.
• (viii) Timing views extraction (.lib) and Library derivation flow
• 2. Logic synthesis:
• (i) Logic synthesis.
• (ii) Event driven simulation of VHDL RTL and Verilog gatelevel netlist
• CAD tools used:
• 1. Encounter (Cadence)
• 2. Virtuoso (Synopsys)
• 3. Synthesis Design Compiler (Synopsys)
• 4. Calibre (Mentor Graphics)
• 5. Incisiv (Cadence)

Jan 2013 – Aug 2013 · 7 mos

• Training in Physical Design. Backend activity done on designs having close to 2.3 million instances in single partitions. Activities like following done:
• (i) Floor Planning
• (ii) Placement
• (iii) CTS
• (iv) Routing
• (vi) Post-routing etc

Jun 2012 – Jul 2012 · 1 mo · Ranchi Area, India

• Training was on Digital Signal Processing. A paper was published under the topic “Study on Effect of Variation of Filter Parameters on Vibration Signal”