Shubham Yadav

Software Engineer

Bengaluru, Karnataka, India4 yrs 2 mos experience
Highly Stable

Key Highlights

  • Expert in Standard Cell Layout Design and VLSI technologies.
  • Proficient in DRC, LVS, and layout verification processes.
  • Strong communication skills with cross-site team collaboration.
Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in VLSI and physical design.

Contact

Skills

Core Skills

Standard Cell Layout DesignPhysical DesignLayout Design

Other Skills

Layout Tool KnowledgeArchitecture ExplorationDRCLVSDFMERCICVP&R KnowledgeCMOS Circuit DesignICV CodingCommunication SkillsSchematic DesignSimulationVery-Large-Scale Integration (VLSI)Semiconductor Fabrication

About

Standard Cell Layout design engineer at Synopsys inc. Contact Details: Email: yadavshubham151@gmail.com

Experience

4 yrs 2 mos
Total Experience
4 yrs 2 mos
Average Tenure
4 yrs 2 mos
Current Experience

Synopsys inc

2 roles

Senior Design Engineer

Dec 2024Present · 1 yr 6 mos

Design Engineer

Apr 2022Dec 2024 · 2 yrs 8 mos

  • Worked on 2nm, 4nm, 8nm, 5nm, 3nm, technodes.
  • Strong Layout tool knowledge (custom compiler (Synopsys)).
  • Architecture exploration of standard cell library.
  • Knowledge of DRC, LVS, DFM, ERC, ICV, and layout development and various PV checks.
  • Knowledge about the impact of standard cell layouts design (pin access point of view) on P&R.
  • Proficient in Standard cells Layout Design and its different verification jobs.
  • Knowledge of P&R at Synopsys tool (ICC II) for abutment mode of cells.
  • Fundamental understanding of technology trade-off in Deep sub-micron.
  • Knowledge of Layout & understanding of CMOS circuit design to improve performance.
  • Hands-on Experience in layouts of various kinds (Logic/Sequential/Power Management/Level shifter/custom and Physical cells).
  • Proficient in ICV Coding.
  • Excellent communication skills and able to work with cross-site teams.
Standard Cell Layout DesignLayout Tool KnowledgeArchitecture ExplorationDRCLVSDFM+7

Ambient scientific

Design Engineer

Jul 2021Aug 2021 · 1 mo · Bangalore Urban, Karnataka, India · On-site

  • Designing of standard cells Schematic, Layout.
  • performed DRC, LVS and simulation of respective using "synopsys CC" Technology - 40nm and Hspice
Schematic DesignLayout DesignDRCLVSSimulationPhysical Design

Haryana

Gurugram police Cyber security internship 2021

Jun 2021Jul 2021 · 1 mo · Gurugram, Haryana, India

  • #GPCSSI'2021

Institution of engineers of india (iei), kolkata

Student Representative

Jun 2018May 2021 · 2 yrs 11 mos · Gurugram, Haryana, India

Education

The NorthCap University

Bachelor of Technology - BTech — Electrical and Electronics Engineering (VLSI)

Jan 2018Jan 2022

Lord Jesus Public School - India

May 2006May 2016

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