Sitaram Alapati

Software Engineer

Hyderabad, Telangana, India9 yrs 8 mos experience

Highly Stable

Key Highlights

Expert in DFT methodologies for complex SoC designs.
Proven track record in delivering scalable DFT solutions.
Strong leadership in cross-functional project execution.

Stackforce AI infers this person is a DFT Engineer specializing in semiconductor design and testing methodologies.

Contact

Skills

Core Skills

DftScan InsertionAtpgEda/cad

Other Skills

Automatic Test Pattern Generation (ATPG)Low Power ATPGMBISTLECTiming SimulationsEDA ToolsLinuxCLPHiringEMIR PoCCompressionDebuggingTessent

About

Seasoned DFT professional with strong expertise in Scan Insertion, ATPG, Simulation, MBIST, and GLS across complex SoC designs. Proven track record of delivering robust and scalable DFT solutions for both Tier-1 semiconductor companies and fast-paced, innovation-driven startups. Experienced in leading end-to-end DFT execution, including resource planning, project coordination, schedule management, and cross-functional collaboration to ensure timely and high-quality silicon delivery. Adept at driving execution efficiency, managing priorities across multiple projects, and supporting production readiness through structured planning and technical leadership. Backed by a solid foundation in EDA tool administration, CAD environment management, and Linux specialization, enabling effective debug, automation, and infrastructure support throughout the chip development lifecycle. Recognized for combining deep technical expertise with strong project management and team collaboration skills to deliver reliable and production-ready solutions.

Experience

9 yrs 8 mos

Total Experience

3 yrs 2 mos

Average Tenure

Current Experience

Insemi technology services pvt. ltd.

3 roles

Lead Engineer-DFT

Promoted

Aug 2022 – Jan 2026 · 3 yrs 5 mos · Hyderabad

Generated scan patterns for SAF (Stuck-At Fault) and TDF (Transition Delay Fault) models, including EXTEST ATPG and simulations, supporting high-quality structural test coverage and silicon readiness.
Performed CLP (Conformal Low Power) checks for DFT to ensure low-power intent compliance and correct implementation across test modes.
Trained and mentored a small team at the client location, focusing on upskilling, task execution quality, and delivery ownership.
Actively participated as an interview panel member for DFT roles, contributing to candidate evaluation and hiring decisions.
Collaborated with cross-functional design and verification teams to ensure smooth DFT integration, debug issues, and improve overall test quality and sign-off readiness.

Automatic Test Pattern Generation (ATPG)Low Power ATPGDFTScan Insertion

Staff Design Engineer

Aug 2021 – Jul 2022 · 11 mos · Hyderabad

Performed MBIST pattern validation to ensure memory integrity, functional correctness, and reliable fault detection across embedded memory instances.
Validated memory test flows using multiple client-specific algorithms and methodologies tailored to project and technology requirements.
Generated and optimized scan patterns for SAF (Stuck-At Fault) and TDF (Transition Delay Fault) models to achieve targeted fault coverage and test efficiency.
Executed Scan Insertion using Tessent DFT tools, enabling structured test architecture integration for complex SoC designs.
Analyzed DFT reports and debugged scan chain, coverage, and pattern-related issues to improve overall test quality and design readiness.
Collaborated with design, verification, and implementation teams to support seamless DFT integration and successful project execution.
Active member of Interview Panel

Senior Design Engineer

Jul 2020 – Jul 2021 · 1 yr · Hyderabad

Performed Scan Insertion using Tessent tools along with integration of OCC (On-Chip Clocking) and EDT (Embedded Deterministic Test) to enable efficient and scalable DFT architecture for complex SoC designs.
Executed MBIST pattern validation and ensured robustness of memory test flows using multiple client-specific algorithms tailored to design requirements.
Performed LEC (Logical Equivalence Checking) across multiple design stages, including RTL vs MBIST-inserted RTL, pre-scan vs post-scan netlists, ensuring functional equivalence and design integrity.
Generated scan patterns for SAF (Stuck-At Fault) and TDF (Transition Delay Fault) models, supporting high-quality structural test coverage and silicon readiness.
Supported DFT PoC activities for EM/IR analysis by providing necessary DFT collaterals and insights to assist power integrity and reliability evaluations.
Collaborated with cross-functional design and verification teams to ensure smooth DFT integration, debug issues, and improve overall test quality and sign-off readiness.

Scan InsertionLECDFT

Vaaluka solutions

Design Engineer II

Apr 2019 – Jul 2020 · 1 yr 3 mos · Hyderabad

Performed ATPG pattern generation and validation for complex SoC designs to achieve targeted fault coverage and test quality goals.
Executed timing-aware and non-timing simulations to validate scan patterns and ensure robust DFT implementation across different test scenarios.
Analyzed simulation results, debugged pattern mismatches, and collaborated with cross-functional teams to resolve DFT and test-related issues efficiently.
Generated and delivered comprehensive test collaterals, including pattern files, reports, and documentation, for smooth integration with ATE workflows.
Worked closely with silicon validation and ATE teams to support bring-up, production testing, and yield improvement activities for successful tape-outs.

Automatic Test Pattern Generation (ATPG)Timing SimulationsDFTATPG

Ineda systems

3 roles

Design Engineer I

Jul 2017 – Mar 2019 · 1 yr 8 mos · Hyderabad

Encouraged and mentored by the Ineda Systems Engineering team to pursue my passion for VLSI, I transitioned from infrastructure engineering into the semiconductor design domain. Leveraging my exposure to the complete Spec-to-Silicon flow, including embedded software integration, I began my journey as a DFT Engineer with hands-on experience in Scan Insertion, ATPG, and simulation activities supporting chip validation and test methodologies.

Systems Engineer (EDA/CAD/Linux Specialist)

Feb 2016 – Jul 2017 · 1 yr 5 mos · Hyderabad

Systems Engineer with expertise in EDA/CAD, Linux administration, and VLSI infrastructure management. Hands-on experience across on-prem data centers, servers, storage, LSF, AWS, and O365, supporting scalable and high-availability engineering environments.

EDA ToolsLinuxEDA/CAD

Intern

Jul 2015 – Jan 2016 · 6 mos · Hyderabad

Started my professional journey at Ineda Systems as an Intern, contributing to the setup and expansion of the organization’s data center infrastructure from the ground up. Worked closely with the engineering team on physical network establishment, server commissioning, inter-data center connectivity, and infrastructure operations across networking, storage, compute servers, and backup environments.