Siva R.

Product Engineer

Bengaluru, Karnataka, India2 yrs 6 mos experience

Key Highlights

3 years of experience in functional verification
Expert in building scalable UVM testbenches
Strong collaboration with design teams

Stackforce AI infers this person is a Semiconductor Verification Engineer with expertise in advanced design methodologies.

Contact

sivanandhareddy1999@gmail.com LinkedIn

Skills

Core Skills

System VerilogUniversal Verification Methodology (uvm)

Other Skills

UVMAXIAPBAHBSPIDigital ElectronicsVerilogC (Programming Language)PerlPython (Programming Language)

About

Senior Verification Engineer with 3 years of experience in functional verification using System Verilog and UVM. Skilled in building scalable UVM testbenches, writing assertions, driving constrained-random testing, and achieving coverage closure for IP and SoC designs. Strong collaborator with design  teams, focused on delivering high-quality, bug-free silicon

Experience

2 yrs 6 mos

Total Experience

1 yr 3 mos

Average Tenure

Current Experience

Leadsoc technologies pvt ltd

DFX Engineer

Aug 2024 – May 2025 · 9 mos · Greater Bengaluru Area · On-site

DFX ENGINEER.
Responsibilities • The SoC had 7 Partitions, worked on block level pattern simulation
and debug.
Handled 3 Blocks.
Developed and promoted patterns from IP to SOC level for
characterization and production tests.

System VerilogUVMAXIAPBAHBUniversal Verification Methodology (UVM)

Ust global technology services (india) private limited

Design and verification

Jan 2022 – Nov 2023 · 1 yr 10 mos · Bangalore Rural, Karnataka, India · On-site

Design Verification and
● Good knowledge in System Verilog and UVM with extensive hands-on experience in
advanced design verification
● Experience with protocols such as AXI, APB, AHB, SPI

System VerilogUVMAXIAPBAHBSPI+1