Soma Sekhar

Software Engineer

Bengaluru, Karnataka, India9 yrs 7 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Expert in ASIC/SoC physical design.
  • Proficient in EDA tools like ICC and Cadence Encounter.
  • Strong background in timing closure and static timing analysis.
Stackforce AI infers this person is a VLSI design engineer with expertise in physical design and EDA tools.

Contact

Skills

Core Skills

Physical DesignTiming Closure

Other Skills

Floor PlanningICCstandard cell placementClock Tree SynthesisStatic Timing AnalysisRoutingfixing transition violationsPTCadence EncounterVHDLCperl

About

M-Tech : Microelectronics and VLSI at NIT Calicut, 2014 - 2016 batch Area of interest : ASIC/SoC physical design EDA Tools : ICC, DC-T, PT& SoC Encounter.

Experience

9 yrs 7 mos
Total Experience
4 yrs 9 mos
Average Tenure
5 yrs 2 mos
Current Experience

Qualcomm

Senior Engineer

Apr 2021Present · 5 yrs 2 mos · Bengaluru, Karnataka, India

Floor PlanningPhysical DesignICCTiming Closurestandard cell placementClock Tree Synthesis+8

Intel corporation

Graphic hardware engineer

Oct 2016Mar 2021 · 4 yrs 5 mos · Bengaluru Area, India

Education

National Institute of Technology

M.Tech — Microelectronicsand VLSI Design

Jan 2014Jan 2016

Andhra University

Bachelor of Engineering (BE)

Jan 2009Jan 2013

red rose public school

ssc

Jan 2005Jan 2007

Visvesvaraya National Institute of Technology

Visvesvaraya National Institute of Technology

Visvesvaraya National Institute of Technology

Stackforce found 100+ more professionals with Physical Design & Timing Closure

Explore similar profiles based on matching skills and experience

Soma Sekhar - Software Engineer | Stackforce