Srinivas S Chauhan — Software Engineer
1. RTL verification using System Verilog, UVM at IP level Subsystem & SOC level. 2.Expertise in Code/functional Coverage, assertions, coverage driven verification and constraint random verification. 3.Worked on Register abstraction layer (RAL) to develop ral model for various modules of the legacy IP from individual block rdls(IPs like CAN, GPIO, I2C, SPI). 4. Protocols - AXI, APB SPI, ethernet.
Stackforce AI infers this person is a VLSI and semiconductor verification expert with extensive experience in functional verification.
Location: Bengaluru, Karnataka, India
Experience: 10 yrs 2 mos
Skills
- Functional Verification
- Low-power Design
Career Highlights
- Expert in RTL verification and UVM methodologies.
- Proficient in low-power design and emulation techniques.
- Strong background in functional verification across multiple protocols.
Work Experience
Sandisk
Principal Engineer (10 mos)
Intel Corporation
SOC Design Verification Engineer (1 yr 4 mos)
AMD
Senior Silicon Design Engineer (1 yr 7 mos)
Silicon Design Engineer 2 (2 yrs 8 mos)
Intel Corporation
Design Verification Engineer (3 yrs 2 mos)
Maven Silicon
Intern (9 mos)
Education
Master’s Degree at Visvesvaraya Technological University
Bachelor’s Degree at P D A College of Engineering, GULBARGA
Associate’s Degree at shree guru indipendent PU college of science
High School at SHAHBAAZ english medium school
