Rakesh yadav

Software Engineer

Hyderabad, Telangana, India11 yrs experience

Highly Stable

Key Highlights

8 years of experience in Physical Design engineering.
Expertise in lower tech nodes from 16nm to 3nm.
Proficient in Cadence Innovus and Synopsys PrimeTime.

Stackforce AI infers this person is a Physical Design Engineer with expertise in VLSI and ASIC design.

Contact

Skills

Core Skills

Mixed-signal Integrated CircuitsPhysical Design

Other Skills

Layout Versus Schematic (LVS)PlaceroutePlacement and routeIntegrated Circuits (IC)DebuggingCadence EncounterApplication-Specific Integrated Circuits (ASIC)Cadence SoftwareVery-Large-Scale Integration (VLSI)PerlTCLLogical equivalence checkingFormal VerificationClock Tree Synthesis

About

8 years of experience as Physical Design engineer having knowledge in lower tech nodes ranging from 16nm to 3nm. Skilled in Floorplan, Place & Route (pnr) using cadence Innovus, and static timing analysis using synopsys primetime. and and Physical verification using calibre. Bachelor's degree focused in Electronics and Communications Engineering from JNTUH.

Experience

11 yrs

Total Experience

3 yrs

Average Tenure

1 yr 11 mos

Current Experience

Quest global

Lead Physical Design Engineer

Jul 2024 – Present · 1 yr 11 mos · Hyderabad, Telangana, India · On-site

Mediatek

Senior Physical Design Engineer

Apr 2023 – Jul 2024 · 1 yr 3 mos · Bengaluru, Karnataka, India · On-site

Layout Versus Schematic (LVS)Mixed-Signal Integrated Circuits

Qualcomm

Physical Design Engineer

May 2018 – Mar 2023 · 4 yrs 10 mos · Noida, Uttar Pradesh, India

Physical DesignPlaceroute

Ibm

Associate Engineer

Mar 2015 – Mar 2018 · 3 yrs · Bengaluru, Karnataka, India · On-site

Stackforce found 100+ more professionals with Mixed-signal Integrated Circuits & Physical Design

Explore similar profiles based on matching skills and experience

VENKAT RAJKUMAR BOMMADENI

Senior Staff Engineer

at Qualcomm

Bengaluru, India13 yrs 6 mos exp

Physical DesignASIC

Harsha Balan

Director, Engineering

at Qualcomm

Bengaluru, India28 yrs 2 mos exp

LeadershipEthernetFunctional VerificationVLSISpec-to-GDS

Abhishek Shende

Engineering Intern

at Radiant Semiconductors

Nagpur, India1 yr 2 mos exp

Physical DesignVLSI DesignDFTATPG

Nickson P Jose

Technical Lead

at HCLTech

Bengaluru, India9 yrs 1 mo exp

Sudhish Pandey

Physical Design Engineer

at Wipro

Noida, India16 yrs 3 mos exp

Physical DesignSoCSynthesisEDA

Murali Mohan R

Principal Engineer

at Broadcom

Bengaluru, India23 yrs 11 mos exp

Processor DesignHardware Performance Verification

Lava Kumar

Director

at Samsung Semiconductor

Bengaluru, India19 yrs 8 mos exp

Team LeadershipSRAM DesignCircuit DesignProject ManagementMemory Design

Vijay Narsinghani

Senior Engineering Manager

at SmartSoC Solutions Pvt Ltd

Bengaluru, India14 yrs 1 mo exp

Technical Project LeadershipSemiconductors