Surendra Yenduri — Software Engineer
> Experienced in System Verilog and UVM over 3 years of hands-on expertise. Proven track record in developing and implementing verification environment, ensuring robust and efficient verification processes while prioritizing a bug-free design. > Experienced on Ethernet features testing > So here is a sneak peak of what I am • Verilog HDL • System Verilog • Universal Verification Methodology(UVM) • Functional verification > Standards • Extensive protocol experience in AMBA APB, AXI4 and Ethernet MII/GMII/XGMII (802.3 2018) > Behavioral Skills: • Active Listener • Leadership skills • Communication skills • Collaborative
Stackforce AI infers this person is a VLSI Design and Verification Engineer with expertise in ASIC development.
Location: Bengaluru, Karnataka, India
Experience: 4 yrs 9 mos
Skills
- System Verilog
- Uvm
Career Highlights
- Over 3 years of expertise in System Verilog and UVM.
- Proven track record in developing verification environments.
- Extensive protocol experience in AMBA APB, AXI4, and Ethernet.
Work Experience
Synopsys Inc
ASIC Digital Design Senior Engineer (1 yr 7 mos)
Tata Elxsi
Senior ASIC Design Verification Engineer (3 yrs 2 mos)
Maven Silicon
Advanced VLSI Design & Verification (6 mos)
Education
Bachelor's degree at Siddharth Institute of Engineering & Technology, Puttur
Diploma at Vasavi polytechnic
SSC at Nehru high school
