Uma B S

Software Engineer

Bengaluru, Karnataka, India8 yrs 6 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in Physical Design for advanced technology nodes
Proficient in Static Timing Analysis and Reliability Verification
Strong background in VLSI Design and ASIC design flow

Stackforce AI infers this person is a VLSI Design Engineer with expertise in Physical Design and ASIC development.

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Skills

Core Skills

Physical DesignStatic Timing Analysis

Other Skills

Digital Circuit DesignASIC Design FlowVerilogLayout Versus Schematic (LVS)Design Rule Checking (DRC)Clock Tree SynthesisPerlTCLPlace & RouteCMOSLow-power DesignCadence InnovusICC/ICC2LinuxFloorplanning

About

Handled multiple blocks of latest gen-graphics core with multi-million gates count as “Partition Execution Owner (PEO)” from Register level synthesis (RLS) to GDSII of 28nm/10nm/14nm/5nm Technology node using Synopsys Design Complier and Synopsys ICC tools Good knowledge on Basic VLSI concepts, floorpanning, Static timing Analysis (STA), Clock tree synthesis (CTS), placement, Routing, LVS, DRC, ERC, Antenna fixing, IR drop, Electromigration (EM). Worked on Physical Verification at IP level as “Layout Partition Execution Owner (LPEO)” using Synopsys IC Validator tool. Handled and fixed violations in the Design Rule Check (DRC), Layout versus Schematic (LVS), Antenna violations at block level using Synopsys ICC, ICC2 tools. Worked on Reliability Verification at block level for fixing violations that includes Electromigration, Dynamic and Static IR drop, Signal heat(SH), power shorts, Disconnected instances (DI). Worked on manual Engineering Change Order (ECO) flow for timing and functionality convergence at Block level using Synopsys Primetime tools.