Vaibhav Ganorkar

Product Engineer

Bengaluru, Karnataka, India3 yrs 9 mos experience
Highly StableAI Enabled

Key Highlights

  • 3+ years in Semiconductor design verification.
  • Expertise in SV & UVM with TCL scripting.
  • Strong debugging skills to identify root causes.
Stackforce AI infers this person is a Semiconductor Design Verification Engineer with expertise in IP and subsystem verification.

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Skills

Core Skills

Verification EngineeringDesign VerificationFunctional Verification

Other Skills

AMBA AHBCoverage IssuesDisplay Port SpecificationsSystemVerilogClaude AiVery-Large-Scale Integration (VLSI)SUBSYSTEM VERIFICATIONDFIMemory ControllersHBMAPBGate Level SimulationEdpCode CoverageSimulation Software

About

Current Role: Senior Design Verification Engineer in MediaTek to verify IP level, Subsytem,SOC level Verification Benches ---------------------------------------------------------------- Teaching Is My Passion✅ Technologist By Profession👨‍💻 ---------------------------------------------------------------- 'Classify, Concentrate and Making It Happen' is my work style. Curiosity is my strong Key! I have a great drive to approach challenges differently and take a creative approach. I work extremely hard to coordinate all of my tiny but significant technical and non-technical leanings in order to reduce issues and boost efficiency. I support crystal-clear planning and efficient implementation, and I belive in TEAM-WORK. 3+ years of experience across various Semiconductor design domains and roles Successfully completed more than 5+ Industrial Projects still now. Technical expertise on SV & UVM including Scripting With TCL ✔️Strong Fundamental Skills to Debug Design at Root Cause. -------------------------------------------------------------------------------------

Experience

3 yrs 9 mos
Total Experience
3 yrs 9 mos
Average Tenure
3 yrs 9 mos
Current Experience

Mediatek

3 roles

Senior Verification Engineer

Jul 2023Present · 2 yrs 11 mos

AMBA AHBCoverage IssuesVerification EngineeringDesign Verification

Senior Design Verification Engineer

Promoted

Sep 2022Present · 3 yrs 9 mos

Design Verification Engineer

Sep 2022Jul 2023 · 10 mos

Display Port SpecificationsSystemVerilogDesign VerificationFunctional Verification

Education

VIT_Vellore Institute of Technology

Master of Technology - MTech — VLSI

Savitribai Phule Pune University

Bachelor of Engineering - BE — Electrical Engineering

Jagrut Junior Sci.College Warud

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