V

VAMSI BODAPATI

Product Engineer

Tirupati Urban, Andhra Pradesh, India0 mo experience

Key Highlights

  • Hands-on experience in SoC verification and UVM methodology.
  • Strong foundation in digital design and RTL simulation.
  • Aspiring VLSI engineer with a passion for semiconductor design.
Stackforce AI infers this person is a VLSI engineer candidate with a focus on semiconductor design and verification.

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Skills

Core Skills

Universal Verification Methodology (uvm)Application-specific Integrated Circuits (asic)

Other Skills

SystemVerilogFunctional VerificationSystem on a Chip (SoC)verification engineerVLSIVLSI DESIGN ENGINEERXilinx ISEMicrosoft OfficePrinted Circuit Board (PCB) DesignInternet of Things (IoT)Embedded SystemsComputer ArchitectureVery-Large-Scale Integration (VLSI)EDAPython (Programming Language)

About

I'm currently working as an SoC Verification Intern at Sion Semiconductors, where I'm gaining hands-on experience in SystemVerilog, UVM, and testbench development for SoC-level designs. With a strong foundation in digital design, Verilog, and exposure to RTL simulation and debugging, I'm actively seeking entry-level roles in ASIC/Design Verification. I’ve also worked on VLSI projects including multipliers, RISC-V pipelined architecture, and ASIC flow implementation. My goal is to contribute to innovative semiconductor design and verification teams and grow into a full-time VLSI engineer.

Experience

0 mo
Total Experience
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Average Tenure
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Current Experience

Sion semiconductors private limited

verification Intern

May 2025Nov 2025 · 6 mos · Bengaluru, Karnataka, India · On-site

  • Selected as a Verification Intern at Sion Semiconductors through their dedicated training initiative, Sion Varsity.
  • Currently undergoing intensive hands-on training in SoC Verification, SystemVerilog, and UVM methodology
  • Learning verification planning, writing testbenches, assertions, and simulating designs using industry tools
  • Collaborating with experienced mentors on real-world verification challenges in the VLSI domain
Universal Verification Methodology (UVM)Application-Specific Integrated Circuits (ASIC)SystemVerilog

Education

SV College of Engineering

Bachelor of Technology - BTech — Electronics and Communications Engineering

Sep 2022May 2025

Government Polytechnic Chandragiri

DIPLOMA — Electronics and Communications Engineering

Jan 2019Jan 2022

Sri Venkateswara Childrens high school

8 - 10th class — HIGH school

Jan 2016Jan 2019

keshava reddy school

1 - 7th class — school

Jan 2009Jan 2016

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