Sep 2017 – Dec 2017 · 3 mos

• Teaching assistant for Digital Programmable devices using System Verilog and FPGAs.

Dec 2016 – May 2017 · 5 mos · Greater Minneapolis-St. Paul Area

• Working under Dr. John Sartori on low power, module oblivious mutli-voltage domain PnR to push the limits of power reduction without reducing performance.

May 2017 – Aug 2017 · 3 mos · San Francisco Bay Area

• Working on custom clock tress and leakage optimization recipes for Soc

Jan 2016 – Jul 2016 · 6 mos · Bangalore, India

• Responsible for timing closure for high frequency cores with multi-million gates using Synopsys libraries and Synopsys tools. Involved with the RnD team to provide feedback on routing and timing issues seen for the libraries.
• Was also responsible for interaction with the customers on field, providing effective solutions and timely support.

Oct 2015 – Dec 2015 · 2 mos

Jul 2013 – Nov 2015 · 2 yrs 4 mos

• Employed as an Associate Engineer ,Physical Design Qualcomm India Pvt. Ltd.
• Handled Floor planning, Placement and Route, CTS, Timing, Noise, Power and Physical Verification responsibilities for 28 nm, 20 nm and 14nm technology nodes.
• Projects:
•  Display Unit - Worked extensively on congestion analysis in a 1.2 million gate design due to aggressive area savings for a 14nm FinFET technology node. Also experimented with various VT flavors to achieve highest power recovery.
•  Navigation Unit - Successfully implemented the navigation unit with lesser than target leakage power and high utilization. Executed hierarchical Hard Macros with additional feedthrough punching.
•  Secure Digital Card (Host) Controller - Worked on high frequency interface timing closure with strict slack margin from pad to the DLL.
•  Baseband Rx (ADC) interface with modem, DAC, PCNOC, Resource and Power Manager - Handled floor planning with multiple memories, fixed challenging noise issues and successfully ensured the completion of four Hard Macros from the DFT netlist to the GDS II stage within one month.

Jun 2012 – Aug 2012 · 2 mos · India

• Worked as a summer intern in the Advanced Science and Technology Division to develop a closed loop embedded prototype for effective jitter correction and wandering of beam due to atmospheric turbulence

Jun 2011 – Jul 2011 · 1 mo · India

• Worked as an intern in the Automation Department NDPL, and studied the working of the SCADA system thus re-enforcing my theoretical knowledge with practical experience
• SCADA (supervisory control and data acquisition) is a system operating with coded signals over communication channels so as to provide control of remote equipment (using typically one communication channel per remote station)