Venu Gopal — Software Engineer

Technologies: TSMC A14, N2, N3P, N3E, N3nm, N5nm, GPDK 45nm and TSMC130nm. Physical Verification Checks: DRC, LVS, PG-Integrity, ERC and Latch-Up. -Worked on Digital Layouts of Standard Cells and Memory Cell Design(ROM, SRAM). -Worked on Analog Layouts of LDO, Op-Amp, BGR, PLL and DAC. CAD Tools: Cadence (Virtuoso L, Virtuoso XL & Virtuoso EXL). Physical Verification Tools: Assura, PVS and Calibre. -Good Understanding of Basics of CMOS Concepts. - Knowledge of Device matching, Signal flow, Shielding, Creating Power Mesh, Reducing the Parasitics. -Good at reliability verification fixes EM/IR and delivered multiple Blocks with IR improvements. -Programing Knowledge in Skill. -Good understanding of Analog layout fundamentals .

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in Analog and Digital Layouts.

Location: Hyderabad, Telangana, India

Experience: 5 yrs 2 mos