Vikram T.

Software Engineer

Bengaluru, Karnataka, India15 yrs 9 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Over 12 years of experience in Functional Verification.
  • Expertise in Pre-Silicon and Post-Silicon Verification.
  • Proficient in System Verilog and UVM methodologies.
Stackforce AI infers this person is a highly skilled ASIC Design Verification Engineer with extensive experience in Functional Verification.

Contact

LinkedIn

Skills

Core Skills

Functional VerificationDo-254Mil-std-1553Ip Level VerificationDft VerificationPattern VerificationGraphics VerificationProtocol Layer VerificationVerification EngineeringAsic Design And Verification

Other Skills

Flight Control SystemsMentoringTeam LeadershipDiscrete input outputAssertionsUniversal Verification Methodology (UVM)Python (Programming Language)DebuggingOVMGate Level SimulationDVTDFT Pattern VerificationConformal LECSystemVerilogLow power verification

About

Having 12+ years of Functional Verification in Front End: 10+ years of IP or Block Level Functional Verification(Pre-Silicon) experience - 2 years of lead experience(Pre-Silicon) and 6 years of individual contributor experience) 2 year's of Pattern Verification(Post-Silicon DFT) - 2 years of lead experience(Post-Silicon). Specialties: System Verilog for Verification, System Verilog Assertions,UVM/VMM for System Verilog, Low Power Verification, DFT Verification, GLS, SOI Review in DO-254 Protocols: MIL-STD-1553, DIO, BSCAN, MISCIO, Graphics(Decompression), USB 3.0(Device) - Protocol Layer, MIPI CSI 3.0(Host) - Protocol Layer, Register level verification for two sub-system modules using VMM. Training Certification: System Verilog and VMM for System Verilog at CVC Pvt. Ltd, Doulos Comprehensive System Verilog and UVM

Experience

15 yrs 9 mos
Total Experience
1 yr 6 mos
Average Tenure
4 yrs 8 mos
Current Experience

Boeing

2 roles

Experienced ASIC Design Verification Engineer

Dec 2023 – Present · 2 yrs 6 mos

  • Worked in ACE and REU in Flight control systems as per the DO-254 Review process in Verification.
  • Supported team as a lead contributor.
Flight Control SystemsDO-254MentoringTeam LeadershipFunctional Verification

Senior ASIC Design Verification Engineer

Oct 2021 – Dec 2023 · 2 yrs 2 mos

  • Worked in MIL-1553 and Discrete I/O Verification requirements for various architectures.
  • Supported team as a lead contributor
Discrete input outputAssertionsTeam LeadershipUniversal Verification Methodology (UVM)MIL-STD-1553Functional Verification

Cerium systems

Project Lead

Sep 2020 – Sep 2021 · 1 yr · Bengaluru, Karnataka, India

  • Involved in Pre-Silicon Verification. Worked for Intel(As a senior contributor).
Python (Programming Language)Debugging

Intel corporation

Lead Verification Consultant

Jun 2019 – Feb 2020 · 8 mos · On-site

  • Worked in IP Level Verification project.
  • Involved in Functional Verification for the feature enhancement.
  • Involved in GLS.
IP Level verificationTeam LeadershipFunctional Verification

Eximius design

Technical Lead

May 2019 – Sep 2020 · 1 yr 4 mos

  • Worked in IP Level Verification projects for: Intel(As a Lead) and Samsung(As a Senior contributor).
OVMTeam LeadershipGate Level SimulationFunctional VerificationIP Level Verification

Amd

Lead Verification consultant

Apr 2017 – Feb 2019 · 1 yr 10 mos · On-site

  • Worked in Pattern Verification (DFT Post-Silicon) for two years.
  • Domains: MISCIO, BSCAN.
DVTDFT Pattern VerificationMISCIOTeam LeadershipBSCANPattern Verification

Mediatek

Verification Consultant

Nov 2016 – Apr 2017 · 5 mos · Bengaluru, Karnataka, India · On-site

Conformal LECLow power verification

L&t technology services (graphene)

Sr. Member Technical Staff

Jan 2016 – May 2019 · 3 yrs 4 mos · Bengaluru, Karnataka, India

  • Worked on DFT-Verification
  • Worked on Design-for-Debug Verification
  • Worked on AMBA AXI4 Assertions.
  • Worked on Conformal LEC and Formality LEC.
  • Having exposure to SOC Level Verification.
DVTDFT Pattern VerificationConformal LECSystemVerilogLow power verificationDFT Verification

Samsung research india

Verification Consultant

Apr 2015 – Dec 2015 · 8 mos · Bengaluru, Karnataka, India · On-site

  • Worked on Graphics(Decompression) using UVM for System Verilog.
  • Developed Testplan.
  • Developed Testbench environment for Decompression unit using UVM
Universal Verification Methodology (UVM)GPUGraphics Verification

L&t technology services limited

ASIC Verification Engineer

Jul 2012 – Nov 2014 · 2 yrs 4 mos · Bengaluru, Karnataka, India

  • Worked on USB 3.0(Device)- Protocol Layer using SV
  • Developed Testcases for the functional verification of Protocol Layer
  • Contributed for the Improvement of the Functional Coverage.
  • Worked on MIPI CSI3.0(Host)- Protocol Layer using SV
  • Developed Testcases for the functional verification of Protocol Layer
  • Developed FCOV Plan and executed it with 100% coverage..
  • Coded Assertions for MIPI CSI 3.0(Host)
USB3.0MIPI CSI 3.0Universal Verification Methodology (UVM)SystemVerilogFunctional coverageMIPI DSI+1

Connexion semiconductors pvt. ltd.,(whizchip design)

Verification Engineer

Mar 2011 – Jul 2012 · 1 yr 4 mos · Bengaluru, Karnataka, India

  • Worked on 10Gigabit Ethernet and twosub-system modules(CROWBAR2,Flow Control)
  • Having fair understanding of PCIe Gen2 (Transaction Layer) spec
  • And, also having fair understanding of DDR2 SDRAM spec.
  • Would be interested to work in PCIe or DDR2 SDRAM.
VMMGigabit EthernetPCIeVerification Engineering

Cvc pvt ltd

ASIC Design and Verification Trainee

May 2010 – Feb 2011 · 9 mos

  • With my interest to work for core domain.
  • Shifted from IT domain to Core domain
  • Trained & Certified in System Verilog and VMM for System Verilog.
VMMAssertion Based VerificationSystemVerilogASIC Design and Verification

Tech mahindra

Software Engineer

Nov 2009 – Mar 2010 · 4 mos · Pune/Pimpri-Chinchwad Area

  • Got placed in college placement.
  • Got trained in SQL

Education

Visvesvaraya Technological University

B.E — Telecommunication Engineering

Jan 2004 – Jan 2008

BMS Institute of Technology and Management

Bachelor's degree — Telecommunications Engineering

Jan 2008 – Present

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