Vinod Singh — Operations Associate

M.Tech student in Microelectronics & VLSI Circuits at IIT Kharagpur with hands-on experience in Digital VLSI, RTL Design, SoC Integration, and ASIC Design Flow. Passionate about building reliable and high-performance digital systems through RTL implementation, synthesis, and protocol-based architectures. Worked on AXI4/AXI4-Lite/AXI4-Stream protocols, asynchronous FIFO design, DMA subsystem implementation, Cortex-M7 synthesis on 32nm technology, and SPI communication protocol design in Verilog/SystemVerilog. Familiar with synthesis, STA analysis, timing closure concepts, and QoR evaluation using Synopsys Design Vision and Vivado. Previously worked in DFCCIL under the Ministry of Railways, contributing to commissioning and maintenance of signalling & telecom systems for safe train operations. Actively seeking opportunities in Digital VLSI, RTL Design, ASIC Design Verification, and SoC Design domains or any Digital VLSI domain profile roles.

Stackforce AI infers this person is a Digital VLSI Engineer with expertise in ASIC Design and Railway Telecommunications.

Location: Kharagpur, West Bengal, India

Experience: 5 yrs 9 mos