Kunal Saraswat — Software Engineer

I’m a Physical Design Engineer at AndGate Informatics, passionate about backend chip implementation, design automation, and building AI-assisted EDA workflows. Trained at PINE Training Academy, I gained hands-on experience across the complete Physical Design flow using Cadence Innovus, Genus, and Tempus, covering: Synthesis ▸ Floorplan ▸ Placement ▸ CTS ▸ Routing ▸ STA ▸ Timing & Power Closure Alongside industry experience, I’ve built a strong engineering toolkit through self-driven learning and specialized projects, including: TCL FORGE — a full-stack Tcl learning platform (subscription version launching soon) 20+ Python & Web-based EDA tools — including STA Visualizer, Synthesis Dashboard, Netlist Explorer, and Power Planner Early contributions toward AI-powered verification/optimization engines at AndGate I don’t just execute PD flows — I automate, optimize, and elevate them. Always learning, building, and pushing the boundaries of silicon efficiency and next-gen EDA innovation.

Stackforce AI infers this person is a Physical Design Engineer specializing in EDA tools and automation within the semiconductor industry.

Location: Noida, Uttar Pradesh, India

Experience: 6 yrs 4 mos